112 Gb/s SerDes电路关键技术综述

董春雷; 赵博; 吕平; 李沛杰; 张霞

doi:10.20193/j.ices2097-4191.2025.0010

PDF(948 KB)

集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (10) : 47-54. DOI: 10.20193/j.ices2097-4191.2025.0010

研究论文

112 Gb/s SerDes电路关键技术综述

作者信息 +

Review for 112 Gb/s SerDes circuit key technology

Author information +

文章历史 +

摘要

高速SerDes速率已从56 Gb/s发展到112 Gb/s甚至更高,如何在超高速率下保持信号的完整性,同时实现功耗、可靠性、灵活性和成本效益之间的平衡,是当前研究的热点。基于当前主流的模/数转换和数字信号处理架构,从发送器、接收器、时钟结构及低功耗技术四个方面深入探讨了112 Gb/s SerDes相关关键技术的最新研究进展,并对未来的研究方向进行了展望。

Abstract

High-speed SerDes rates have progressed from 56 Gb/s to 112 Gb/s and beyond. Maintaining signal integrity at such ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. This paper reviews key technologies for 112 Gb/s SerDes from four perspectives: transmitter, receiver, clock structure, and low-power techniques, based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.

导出引用

董春雷, 赵博, 吕平, 等. 112 Gb/s SerDes电路关键技术综述[J]. 集成电路与嵌入式系统. 2025, 25(10): 47-54 https://doi.org/10.20193/j.ices2097-4191.2025.0010

DONG Chunlei, ZHAO Bo, LYU Ping, et al. Review for 112 Gb/s SerDes circuit key technology[J]. Integrated Circuits and Embedded Systems. 2025, 25(10): 47-54 https://doi.org/10.20193/j.ices2097-4191.2025.0010

中图分类号： TN40 (一般性问题)

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