Design of image processing system based on high-speed serial buses and DSP+FPGA architecture

LI Peibin

doi:10.20193/j.ices2097-4191.2024.0033

PDF(11645 KB)

Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (12) : 45-51. DOI: 10.20193/j.ices2097-4191.2024.0033

Research Paper

Design of image processing system based on high-speed serial buses and DSP+FPGA architecture

LI Peibin ^*

Author information +

History +

Abstract

The high-performance DSP+FPGA architecture can meet the real-time processing requirements of the embedded image processing system for large amounts of data and complex algorithms. The traditional DSP+FPGA architecture uses the parallel external memory interface as the data transfer interface, with a large number of traces, difficult PCB wiring, and many failure points. The use of high-speed serial buses can solve the above problems. This paper proposes an image processing system based on high-speed serial buses and DSP+FPGA architecture. PCIe bus is used as the image data channel between DSP and FPGA, SRIO bus is used as the link between DSP and DSP, and SGMII bus is used as the data channel between DSP and PHY chip. High-speed serial buses enable faster the data transfer rate, easier layout of the PCB, lower electromagnetic interference, and better noise immunity. The system designed in this paper has been deployed and operated stably in practical locations, which demonstrates that the design is feasible and the system is reliable.

Key words

high-speed serial bus / PCIe / DSP / FPGA / DSP+FPGA architecture

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

LI Peibin. Design of image processing system based on high-speed serial buses and DSP+FPGA architecture[J]. Integrated Circuits and Embedded Systems. 2024, 24(12): 45-51 https://doi.org/10.20193/j.ices2097-4191.2024.0033

References

List( Publishing order | Descend order by publishing year | Descend order by cited within ) Chart analysis

[1]	李士杰, 马瑞昌, 邓明兴, 等. JESD204C高速串行接口电路设计技术[J]. 微纳电子与智能制造, 2023, 5(3):14-21. LI S J, MA R C, DENG M X, et al. Design technique for JESD204C high-speed serial interface circuit[J]. Micro/nano Electronics and Intelligent Manufacturing, 2023, 5(3):14-21 (in Chinese). Cited in this article [1]

[2]	章燕妮. 基于高速串行总线技术的质谱仪控制系统的研发[D]. 杭州: 中国计量大学, 2023. ZHANG Y N. Development of mass spectrometer control system based on high-speed serial bus technology[D]. Hangzhou: China Jiliang University, 2023 (in Chinese). Cited in this article [1]

[3]	田之俊, 冯晓文, 赵超, 等. 测控系统高速串行数据传输缓存技术研究[J]. 无线电通信技术, 2023, 49(2):286-291. TIAN Z J, FENG X W, ZHAO C, et al. A high-speed transmission data cache method for measurement and control system[J]. Radio Communications Technology, 2023, 49(2):286-291 (in Chinese). Cited in this article [1]

[4]	马贤. 基于FPGA的高速数据传输接口设计[D]. 桂林: 桂林电子科技大学, 2023. MA X. Design of high-speed data transmission interface based on FPGA[D]. Guilin:Guilin University of Electronic Technology, 2023 (in Chinese). Cited in this article [1]

[5]

刘凯文. 基于sigrity仿真工具的高速串行信号的分析与设计[D]. 北京: 中国科学院大学(中国科学院光电技术研究所), 2023.

LIU

K W

. Analysis and design of high speed serial signal based on sigrity simulation tool[D]. Beijing: University of Chinese Academy of Sciences (Institute of Optics and Electronics, Chinese Academy of Sciences), 2023 (in Chinese).

Cited in this article [1]

[6]

魏同成, 杜勇, 左杨. DSP+FPGA的EMIF通信系统设计与实现[J]. 新疆师范大学学报(自然科学版), 2023, 42(1):14-24.

WEI

T C

, DU

, ZUO

. Design and implementation of EMIF communication system based on DSP+FPGA[J]. Journal of Xinjiang Normal University (Natural Sciences Edition), 2023, 42(1):14-24 (in Chinese).

Cited in this article [1]

[7]	王笑寒, 韩文波. 基于FPGA+DSP的高清视频监控系统研究[J]. 长春理工大学学报(自然科学版), 2022, 45(6):67-72. WANG X H, HAN W B. Research on HD video surveillance system based on FPGA+DSP[J]. Journal of Changchun University of Science and Technology (Natural Science Edition), 2022, 45(6):67-72 (in Chinese). Cited in this article [1]

[8]	李晓宇. 基于FPGA+DSP的光纤数据传输电路设计[D]. 太原: 中北大学, 2023. LI X Y. Design of optical fiber data transmission circuit based on FPGA+DSP[D]. Taiyuan: North University of China, 2023 (in Chinese). Cited in this article [1]

[9]	李佩斌, 黄莹, 赵誉婷. 基于DSP+FPGA的嵌入式图像处理系统设计[J]. 现代电子技术, 2014, 37(20):95-98. LI P B, HUANG Y, ZHAO Y T. Design of embedded image processing system based on DSP+FPGA architecture[J]. Modern Electronics Technique, 2014, 37(20):95-98 (in Chinese). Cited in this article [2]

[10]	李倩. 基于低抖动锁相环高速串行接口的研究[D]. 成都: 电子科技大学, 2023. LI Q. A study of high-speed serial interfaces based on low-jitter phase-locked loops[D]. Chengdu: University of Electronic Science and Technology of China, 2023 (in Chinese). Cited in this article [1]

[11]	束正武. 基于28 nm工艺的16Gbps_SerDes_TX电路研究与设计[D]. 南京: 南京邮电大学, 2023. SHU Z W. Research and design of 16Gbps_SerDes_TX circuit based on 28nm process[D]. Nanjing: Nanjing University of Posts and Telecommunications, 2023 (in Chinese). Cited in this article [1]

[12]	陈子豪. 12.5 Gb/s SerDes系统接收端自适应均衡器设计[D]. 南京: 东南大学, 2022. CHEN Z H. Design of an adaptive equalizer at the receiver of 12.5 GB/S SerDes system[D]. Nanjing: Southeast University, 2022 (in Chinese). Cited in this article [1]

[13]	李兆祯. 基于UVM的高速串行SerDes验证[D]. 西安: 西安电子科技大学, 2022. LI Z Z. High-speed serial SerDes verification based on UVM[D]. Xi`an: Xidian University, 2022 (in Chinese). Cited in this article [1]

[14]	薛培, 官剑, 邵春伟, 等. 基于FPGA的SRIO多通道控制系统设计与实现[J]. 电子技术应用, 2023, 49(1):107-113. XUE P, GUAN J, SHAO C W, et al. Design and implementation of SRIO multiple channel control system based on FPGA[J]. Application of Electronic Technique, 2023, 49(1):107-113 (in Chinese). Cited in this article [1]

[15]	兰唯, 韩延喆, 扈啸. 基于FPGA的千兆以太网端口通信设计[J]. 电子科技, 2024, 37(1):48-54. LAN W, HAN Y Z, HU X. Design of gigabit Ethernet port communication base on FPGA[J]. Electronic Sci. & Tech., 2024, 37(1):48-54 (in Chinese). Cited in this article [1]

[16]	王羽琪. 基于PCIe的通信协议栈硬件加速方案设计与实现[D]. 北京: 北京邮电大学, 2024. WANG Y Q. Design and implementation of PCIe-based communication protocol stack hardware acceleration schema[D]. Beijing: Beijing University of Posts and Telecommmunications, 2024 (in Chinese). Cited in this article [1]

[17]

李龙乾, 方华, 冯姣, 等. 基于FPGA的PCIe接口逻辑设计与实现[J]. 太赫兹科学与电子信息学报, 2022, 20(4):385-392.

L Q

, FANG

, FENG

, et al. Design and implementation of PCIe interface logic based on FPGA[J]. Journal of Terahertz Science and Electronic Information Technology, 2022, 20(4):385-392 (in Chinese).

Cited in this article [1]

[18]	洪畅, 翟栋梁, 丁志辉. 一种基于PCIE总线的高性能数据传输架构设计[J]. 现代电子技术, 2023, 46(21):6-10. HONG C, ZHAI D L, DING Z H. Design of high-performance data transmission architecture based on PCI-express bus[J]. Modern Electronics Technique, 2023, 46(21):6-10 (in Chinese). Cited in this article [1]

[19]	刘拓. 基于FPGA的高速存储器数据传输接口设计与实现[D]. 西安: 西安电子科技大学, 2022. LIU T. Design and implementation of high-speed memory data transmission interface based on FPGA[D]. Xi`an: Xidian University, 2022 (in Chinese). Cited in this article [1]