Design of image processing system based on high-speed serial buses and DSP+FPGA architecture

LI Peibin

Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (12) : 45-51.

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PDF(11645 KB)
Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (12) : 45-51. DOI: 10.20193/j.ices2097-4191.2024.0033
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Design of image processing system based on high-speed serial buses and DSP+FPGA architecture

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 24(12): 45-51 https://doi.org/10.20193/j.ices2097-4191.2024.0033

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