Timing optimization design of ASIC chip based on buffer

ZHANG Xiang, ZHAO Qilin

Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (12) : 33-37.

PDF(909 KB)
PDF(909 KB)
Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (12) : 33-37. DOI: 10.20193/j.ices2097-4191.2024.0046
Research Paper

Timing optimization design of ASIC chip based on buffer

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +
History +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 24(12): 33-37 https://doi.org/10.20193/j.ices2097-4191.2024.0046

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(909 KB)

Accesses

Citation

Detail
Sections
Recommended

/

〈 〉