With the rapid development of very large-scale integration IC manufacturing process and the continuous improvement of integration, the difficulty of chip timing convergence has become increasingly prominent. The significance of timing, as one of the core indexes in the physical design of digital chips, cannot be underestimated. In integrated circuit design, buffers are added to optimize fan-out and reduce interconnect latency, thereby improving timing performance. However, due to the limitations of EDA tools in predicting the position of standard cells, the method of automatically inserting buffers may be unreasonable. This study conducted an in-depth exploration of the placement and route design of an ASIC chip using Innovus as a design tool. During the placement stage, an optimized method targeted at buffer insertion was employed. The experimental results indicate that this method significantly improved the design result after placement and route, accelerating the time sequence convergence process.