To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores, a phased, self-designed approach is proposed to add AXI bus support to a designed MIPS processor core. The design is implemented using Verilog HDL for writing RTL code. The overall logic functionality of the processor was verified in the Vivado simulation environment, and the bitstream file was downloaded to the FPGA development board for prototype verification to obtain utilization and timing. Finally, the processor is synthesized using the Design Compiler (DC) tool, and the overall area and power consumption of the processor are evaluated. The verification results indicate that the self-designed AXI bus consumes fewer resources and occupies less area compared to directly using an AXI interface IP core. Furthermore, this approach ensures that the AXI bus is added without changing the processor core architecture, significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface. It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.