An adaptive continue time liner equalizer for laser diode driver in the aerospace date communications

LYU Chen, CHEN Lei, FENG Changlei, ZHOU Ji, SUN Shanshan, QIN Zhibin, LI Yanyan

Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (1) : 12-17.

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Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (1) : 12-17. DOI: 10.20193/j.ices2097-4191.2024.0069
Special Topic of Aerospace Component Reliability

An adaptive continue time liner equalizer for laser diode driver in the aerospace date communications

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Abstract

As the rapid growth of the signal bandwidth in aerospace data communications, the data rate of laser diode driver(LDD) in aerospace optical fiber communication has enter the era of hundred-gigabits. For the sake of radiation harden and high reliability design, the introduction of extra parasitic factor requires more efforts in the circuit design to compensate the loss of bandwidth at high frequency. This work proposes an adaptive continue time linear equalizer(CTLE) which is based on a SiGe BiCMOS platform giving a programmable loss compensating capability up to 16 dB at 14 GHz.It has the capable of adaptive gain compensation adjustment, supporting up to 25 Gb/s NRZ signal transmission.

Key words

laser driver / aerospace optical module / continuous time equalizer / high-pass filter / low-pass filter

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LYU Chen , CHEN Lei , FENG Changlei , et al . An adaptive continue time liner equalizer for laser diode driver in the aerospace date communications[J]. Integrated Circuits and Embedded Systems. 2025, 25(1): 12-17 https://doi.org/10.20193/j.ices2097-4191.2024.0069

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