Thermal simulation assessment of assembly process of fan-out wafer level package based on finite element analysis

LI Peilei, ZHANG Wei, JIA Qiuyang, JIANG Maogong, GU Hantian

Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (7) : 37-42.

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Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (7) : 37-42. DOI: 10.20193/j.ices2097-4191.2024.07.006
Special Topic of Integrated Circuits Reliability

Thermal simulation assessment of assembly process of fan-out wafer level package based on finite element analysis

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Abstract

This paper evaluates the thermal reliability of assembly process of Fan-out Wafer Level Package based on simulation. Firstly, we briefly introduce the critical technologies of Fan-out wafer level package and analyze the possible failure mechanism of these advanced packaging technologies. Then, for a typical package structure based on Fan-out wafer level package technology, the 1/4 structure finite element model is established. The simulation of the critical structure under the typical military thermal cycling condition is conducted. By analyzing the stress and displacement of the key structures of the package, potential reliability vulnerabilities leading to failure of fan-out wafer-level packaging have been identified.

Key words

wafer level package / reliability / thermal cycling / finite element analysis / TSV

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LI Peilei , ZHANG Wei , JIA Qiuyang , et al . Thermal simulation assessment of assembly process of fan-out wafer level package based on finite element analysis[J]. Integrated Circuits and Embedded Systems. 2024, 24(7): 37-42 https://doi.org/10.20193/j.ices2097-4191.2024.07.006

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