Processing unit design for high-performance computing processors

LIU Yu; ZHANG Jie; ZHOU Le

doi:10.20193/j.ices2097-4191.2025.0039

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Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (9) : 57-62. DOI: 10.20193/j.ices2097-4191.2025.0039

Research Paper

Processing unit design for high-performance computing processors

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Abstract

This paper proposes a design for a compute-in-memory processing unit (CIMPU) tailored for high-performance computing processors. The CIMPU integrates a multi-precision arithmetic operator and on-chip storage, enabling computations to be performed locally without accessing external buses. A hardware pipeline is further designed based on the CIMPU's architectural characteristics to optimize processing efficiency. The operation unit design scheme proposed in this paper has a good performance-power-consumption ratio advantage. We evaluated the computational performance of the design, with a performance to power ratio of 2.47 TOPS/W@INT8. It is significantly superior to other similar processor architectures and is suitable for large-scale deployment as a high computing power processor core.

Key words

high-performance computing processor / processing unit / scalability / pipeline / FPGA

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LIU Yu , ZHANG Jie , ZHOU Le. Processing unit design for high-performance computing processors[J]. Integrated Circuits and Embedded Systems. 2025, 25(9): 57-62 https://doi.org/10.20193/j.ices2097-4191.2025.0039

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