Design of a high-speed multi-channel synchronous acquisition system

DONG Weitao; WU Yunsheng; XU Li; ZHANG Chao; LI Hangyu

doi:10.20193/j.ices2097-4191.2025.0040

PDF(4528 KB)

Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (10) : 55-60. DOI: 10.20193/j.ices2097-4191.2025.0040

Research Paper

Design of a high-speed multi-channel synchronous acquisition system

Author information +

History +

Abstract

For application scenarios requiring multi-channel high-speed acquisition and stable synchronization between channels, a multi-channel synchronous acquisition scheme based on Field-Programmable Gate Array (FPGA) is designed and implemented. This scheme adopts FPGA as the control and processing core, employs high-speed Analog-to-Digital Converters (ADC) to build sampling channels, and designs a stable clock and synchronization scheme, thus realizing a multi-channel synchronous acquisition system under high sampling rates. The feature of this solution is that it can monitor and adjust the synchronization status among multiple channels in real time, and it can be conveniently extended to synchronous acquisition among boards. The test results show that the data collected across all channels remains stably synchronized every time the system is powered on or off.

Key words

acquisition synchronization between channels / FPGA / ADC

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

DONG Weitao , WU Yunsheng , XU Li , et al . Design of a high-speed multi-channel synchronous acquisition system[J]. Integrated Circuits and Embedded Systems. 2025, 25(10): 55-60 https://doi.org/10.20193/j.ices2097-4191.2025.0040

References

List( Publishing order | Descend order by publishing year | Descend order by cited within ) Chart analysis

[1]	王德恒, 刘文政. 基于AD9208的高速采集电路设计[J]. 舰船电子对抗, 2021(1):108-111. WANG D H, LIU W Z. Design of High-speed Acquisition Circuit Based on AD9208[J]. Shipboard Electronic Countermeasure, 2021(1):108-111 (in Chinese). Cited in this article [1]

[2]	王浩, 李琛, 李侠, 等. 一款20位无噪声分辨率ADC设计与测试[J]. 中国集成电路, 2021(4):50-57. WANG H, LI C, LI X, et al. Design and Test of a 20bit Noise-Free Resolution ADC[J]. China Integrated Circult, 2021(4):50-57 (in Chinese). Cited in this article [1]

[3]	李海涛, 李斌康, 田耕, 等. 基于JESD204B的1GS/s、16-bit数据采集系统研究[J]. 电子技术应用, 2021, 47(4):126-131. LI H T, LI B K, TIAN G, et al. Research on 1 GS/s, 16-bit data acquisition system based on JESD204B[J]. Application of Electronic Technique, 2021, 47(4):126-131 (in Chinese). Cited in this article [1]

[4]	王宽敏, 刘文怡. 基于FPGA的多通道高速信号同步采集系统[J]. 仪表技术与传感器, 2025(1):79-84. WANG K M, LIU W Y. Multi-channel High Speed Signal Synchronization Acquisition System Based on FPGA[J]. Instrument Technique and Sensor, 2025(1):79-84 (in Chinese). Cited in this article [1]

[5]	李小龙, 江虹, 罗颖, 等. 基于FPGA的小信号高精度采集系统设计[J]. 传感器与微系统, 2024, 43(5):79-82. LI X L, JIANG H, LUO Y, et al. Design of small signal high precision acquisition system based on FPGA[J]. Transducer and Microsystem Technologies, 2024, 43(5):79-82 (in Chinese). Cited in this article [1]

[6]	孙磊, 张松柏. 基于JESD204B协议的多板卡同步采样设计与实现[J]. 船舰电子对抗, 2021(4):104-107. SUN L, ZHANG S B. Design and Implement of Synchronization Sampling on Multiple Boards Based on JESD204B Protocol[J]. Shipboard Electronic Countermeasure, 2021(4):104-107 (in Chinese). Cited in this article [1]

[7]	张彤, 张金凤, 孟爱权, 等. 基于FPGA的多片ADC同步设计与实现[J]. 火控雷达技术, 2024, 53(1):72-75,91. ZHANG T, ZHANG J F, MENG A Q, et al. Design and Implementation of Multi-chip ADC Synchronization Based on FPGA[J]. Fire Control Radar Technology, 2024, 53(1):72-75,91 (in Chinese). Cited in this article [1]

[8]	张明春. 基于JESD204B协议的发送端高速串行接口电路设计[D]. 重庆: 重庆理工大学, 2024. ZHANG M C. Designing a high-speed serial interface circuit utilizing the JESD204B protocol[D]. Chongqing: Chongqing University of Technology, 2024 (in Chinese). Cited in this article [1]

[9]	赵瑜婕, 李杰, 张德彪, 等. 基于JESD204B的数据采集存储系统的设计[J]. 自动化与仪表, 2025(1):132-136. ZHAO Y J, LI J, ZHANG D B, et al. Design of Data Acquisition and Storage System Based on JESD204B[J]. Automation & Instrumentation, 2025(1):132-136 (in Chinese). Cited in this article [1]

[10]	JEDEC solid state technologyassociation. Serial Interface for Data Converters. Revision JES D204,U.S.A:North 10th Street Suite 240 South Arlington, 2006.20-200. Cited in this article [1]

[11]	JEDEC solid state technology association. Serial Interface for Data Converters. Revision JES D204B -01,U.S.A:North 10th Street Suite 240 South Arlington, 2012.13-220. Cited in this article [1]