低压超大功率PCB电源完整性分析

陈光; 王刚; 贾春波

doi:10.20193/j.ices2097-4191.2024.0084

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集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (3) : 1-8. DOI: 10.20193/j.ices2097-4191.2024.0084

封面文章

低压超大功率PCB电源完整性分析

陈光 ¹ ,
王刚 ² ,
贾春波 ¹^,^*

作者信息 +

Analysis of power integrity for low-voltage high-power PCB

CHEN Guang ¹ ,
WANG Gang ² ,
JIA Chunbo ¹^,^*

Author information +

文章历史 +

摘要

针对48 V输入电压、0.8 V输出电压及1 000 A电流需求的国产电源验证板的布局布线设计,开展电源完整性分析。提出了一种基于电源分配网络(PDN)的仿真设计策略,即在最初阶段,通过对比不同PCB布局的电压降仿真结果选择良好布局,再通过电源平面及过孔载流的仿真分析对过流过孔进行优化设计。优化措施使电压跌落降低了14.5 mV,平面电路密度减小了61%,电源系统损耗降低了17.2 W,并减缓过孔电流至1/2。此外,模拟了使用散热器的热效应,结果显示散热器应用后最高温度下降了27.81 ℃。最后,使用电源平面谐振仿真分析,成功将电源平面谐振噪声控制在输出电压的0.001%以内。实测结果表明,验证板纹波噪声控制在额定输出电压的1%以内,整体效率超过90%,达到行业领先水平。本文所提出的仿真流程策略能有效提高PCB设计效率,避免了过大的降压损失、过流及过温等电源完整性风险。

Abstract

A power integrity analysis is conducted for the layout and routing design of a domestic power verification board targeting a 48 V power input, with an output voltage of 0.8 V and a current requirement of 1 000 A. A simulation design strategy based on the power distribution network (PDN) is proposed. In the initial stage, an optimal layout is selected by comparing the voltage drop simulation results with different PCB layouts. Then, through simulation analysis of the power plane and via current carrying capacity, the vias are optimized. The optimization measures significantly reduced the voltage drop by 14.5 mV, decreased the plane circuit density by 61%, lowered power system loss by 17.2 W, and halved the via current. Moreover, the thermal effect of using a heat sink is simulated, and the results show that the highest temperature dropped by 27.81 ℃ after the application of the heat sink. Finally, using power plane resonance simulation analysis, the power plane resonance noise is successfully controlled within 0.001% of the output voltage. After board fabrication and actual measurement, the ripple noise of the verification board was controlled within 1% of the rated output voltage, and the overall efficiency exceeded 90%, reaching an industry-leading level. The results indicate that the simulation process strategy proposed in this paper can effectively improve the efficiency of PCB design, and avoid power integrity risks, such as excessive voltage drop loss, overcurrent, and overheating.

导出引用

陈光, 王刚, 贾春波. 低压超大功率PCB电源完整性分析[J]. 集成电路与嵌入式系统. 2025, 25(3): 1-8 https://doi.org/10.20193/j.ices2097-4191.2024.0084

CHEN Guang, WANG Gang, JIA Chunbo. Analysis of power integrity for low-voltage high-power PCB[J]. Integrated Circuits and Embedded Systems. 2025, 25(3): 1-8 https://doi.org/10.20193/j.ices2097-4191.2024.0084

中图分类号： TP931

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