DSP的PCIe安全式自启动技术研究

颜川; 宋超

doi:10.20193/j.ices2097-4191.2024.04.007

PDF(1440 KB)

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (4) : 42-46. DOI: 10.20193/j.ices2097-4191.2024.04.007

研究论文

DSP的PCIe安全式自启动技术研究

颜川 ^* ,
宋超

作者信息 +

Research on PCIe secure self-start technology based on DSP

YAN Chuan ^* ,
SONG Chao

Author information +

文章历史 +

摘要

数字信号处理芯片是一类运算速度极快、运算资源丰富的微型处理器。DSP凭借强大的运算性能在图像处理、大数据高性能运算领域发挥着核心作用。自启动技术是DSP芯片应用的关键技术之一。高性能DSP芯片通常会集成PCIe这一通用性高速外设。本文针对使用PCIe技术用于DSP芯片引导启动开展研究,设计并实现了一种可用于高性能DSP芯片的PCIe安全模式自启动引导方案。

Abstract

Digital Signal Processing (DSP) chips are a class of microprocessors that boast lightning-fast computational speeds and an abundance of computational resources.Leveraging their exceptional processing capabilities,DSP plays an important role in the domains of image processing and high-performance computing in big data.Among the key technologies employed in DSP chip applications,self-starting technology stands out as a critical component.Moreover,high-performance DSP chips often integrate PCIe,a high-speed universal peripheral,to enhance their processing capabilities.In the article,we present a research that focuses on the design and implementation of a PCIe secure self-starting boot scheme for high-performance DSP chips.The secure solution holds significant potential for use in the development of high-performance DSP chips.

导出引用

颜川, 宋超. DSP的PCIe安全式自启动技术研究[J]. 集成电路与嵌入式系统. 2024, 24(4): 42-46 https://doi.org/10.20193/j.ices2097-4191.2024.04.007

YAN Chuan, SONG Chao. Research on PCIe secure self-start technology based on DSP[J]. Integrated Circuits and Embedded Systems. 2024, 24(4): 42-46 https://doi.org/10.20193/j.ices2097-4191.2024.04.007

中图分类号： TP311 (程序设计、软件工程) TN492 (专用集成电路)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]

甄国涌, 苏慧思, 陈建军, 等. 基于FPGA的PCIe接口的数据传输设计与实现[J]. 国外电子测量技术, 2021(12): 40.DOI:10.19652/j.cnki.femt.2102917.

ZHEN

G Y

, SU

H S

, CHEN

J J

, et al. Design and Implementation of Data Transmission via PCIe Interface Based on FPGA[J]. Foreign Electronic Measurement Technology, 2021(12): 40.DOI:10.19652/j.cnki.femt.2102917. (in Chinese)

本文引用 [1]

[2]	SHARMAD D. PCI Express 6.0 Specification:A Low-Latency,High-Bandwidth,High-Reliability,and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling[J]. IEEE Micro, 2021(1):41. 本文引用 [1]

[3]	李文磊. 基于PCIE总线的高速数据传输系统的设计与实现[D]. 成都: 电子科技大学, 2016. LI W L. Design and Implementation of High-Speed Data Transmission System Based on PCIe Bus[D]. Chengdu: University of Electronic Science and Technology, 2016. (in Chinese) 本文引用 [2]

[4]	杨露, 张荣, 张梅娟, 等. 基于PowerPC架构的二级启动设计[J]. 电子与封装, 2020, 20(3):4.DOI:CNKI:SUN:DYFZ.0.2020-03-008. YANG L, ZHANG R, ZHANG M J, et al. Design of Secondary Boot Based on PowerPC Architecture[J]. Electronics and Packaging, 2020, 20(3):4.DOI: CNKI:SUN:DYFZ.0.2020-03-008. (in Chinese) 本文引用 [1]

[5]

王法臻, 崔少辉, 王成. PCIe设备驱动程序开发的关键技术[J]. 现代电子技术, 2021, 44(16):65-69.DOI:10.16652/j.issn.1004-373x.2021.16.013.

WANG

F ZH

, CUI

SH H

, WANG

. Key Technologies in PCIe Device Driver Development[J]. Modern Electronics Technology, 2021, 44(16):65-69.DOI:10.16652/j.issn.1004-373x.2021.16.013. (in Chinese)

本文引用 [3]

[6]

张乐年, 关榆君. 基于TMS320C6678的多核DSP加载模式研究[J]. 电子设计工程, 2013, 21(24):5.DOI:10.3969/j.issn.1674-6236.2013.24.050.

ZHANG

L N

, GUAN

Y J

. Research on multi-core DSP loading mode based on TMS320C6678[J]. Electronic Design Engineering, 2013, 21(24):5.DOI:10.3969/j.issn.1674-6236.2013.24.050. (in Chinese)

本文引用 [1]

[7]	FERREIRA R S, VARGAS F. ShadowStack:A new approach for secure program execution[J]. Microelectronics Reliability, 2015, 55(9-10):2077-2081.DOI:10.1016/j.microrel. 2015.07.021. https://linkinghub.elsevier.com/retrieve/pii/S0026271415301116 本文引用 [1]

[8]	PCI-Special Interest Group.PCI Express 3.0 Base Specification Revision[S]. PCI-SIG 2010. 本文引用 [2]

[9]	PCI-Special Interest Group.PCI Express 2.0 Base Specification Revision[S]. PCI-SIG 2006. 本文引用 [2]

[10]

张象羽, 施慧莉. 基于以太网和PCIe的多核DSP开发平台[J]. 计算机工程与科学, 2019, 41(10):7.DOI:10.3069/j.issn.1007-130X.2019.10.003.

ZHANG

X Y

, SHI

H L

. Multi-Core DSP Development Platform Based on Ethernet and PCIe[J]. Computer Engineering and Science, 2019, 41(10):7.DOI:10.3069/j.issn.1007-130X.2019.10.003. (in Chinese)

本文引用 [1]

[11]	KAVIANIPOUR H, MUSCHTER S, BOHM C. High Performance FPGA-Based DMA Interface for PCIe[J]. IEEE Transactions on Nuclear Science, 2014, 61(2):745-749. https://doi.org/10.1109/TNS.2014.2304691 http://ieeexplore.ieee.org/document/6786396/ 本文引用 [2]

[12]	王齐. PCI Express体系结构导读[M]. 北京: 机械工业出版社, 2013. WANG Q. Introduction to PCI Express Architecture[M]. Beijing: Machinery Industry Press, 2013. (in Chinese) 本文引用 [2]

[13]

张跃玲, 张磊, 汪健, 等. 一种基于DSP的多核SOC中断扩展设计与实现[J]. 微电子学与计算机, 2016, 33(8):6.DOI:CNKI:SUN:WXYJ.0.2016-08-003.

ZHANG

Y L

, ZHANG

, WANG

, et al. Design and Implementation of Interrupt Extension in DSP-Based Multi-Core SoC[J]. Microelectronics & Computer, 2016, 33(8):6.DOI:CNKI:SUN:WXYJ.0.2016-08-003. (in Chinese)

本文引用 [2]

[14]

赵赛, 闫华, 丛红艳, 等. 基于UVM的PCI Express总线控制器验证平台[J]. 电子与封装, 2022(2): 22.DOI:10.16257/j.cnki.1681-1070.2022.0212.

ZHAO

, YAN

, CONG

H Y

, et al. UVM-Based Verification Platform for PCI Express Bus Controller[J]. Electronics and Packaging, 2022(2): 22.DOI:10.16257/j.cnki.1681-1070.2022.0212. (in Chinese)

本文引用 [2]

[15]	MORGAN B, ALATA E, NICOMETTE V, et al. Bypassing IOMMU Protection against I/O Attacks[C]// Dependable Computing.IEEE, 2016:145-150.DOI:10.1109/LADC.2016.31. 本文引用 [1]