数据转换器中电容失配的分析与解决方案

杨翼好; 刘国骜; 于健睿; 马金戈; 胡远奇

doi:10.20193/j.ices2097-4191.2024.0056

PDF(9938 KB)

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (12) : 1-11. DOI: 10.20193/j.ices2097-4191.2024.0056

封面文章

数据转换器中电容失配的分析与解决方案

杨翼好 ¹^,^# ,
刘国骜 ²^,^# ,
于健睿 ² ,
马金戈 ² ,
胡远奇 ²^,^*

作者信息 +

An analysis for capacitor mismatches in data converters and its solution

YANG Yihao ¹ ,
LIU Guoao ² ,
YU Jianrui ² ,
MA Jinge ² ,
HU Yuanqi ²^,^*

Author information +

文章历史 +

摘要

在高分辨率模/数转换器(ADC)设计中,由于工艺变化导致的电容失配对精度有很大影响,业内为了解决这一问题提出了许多补偿方法,但通常需要添加额外的电路或外部控制器,增大了硅片面积和操作复杂度。本文分析并确定了电容失配、输出偏差和总谐波失真(THD)在电容型数/模转换器(DAC)中的关系,并推导出THD在特定失配条件下的分布情况,可用于评估ADC在电容失配下的性能边界。在此基础上,本文提出了一种采用动态元素匹配(DEM)技术的新型补偿方法,并以最小的硬件成本在循环型流水线ADC中实现,流片测试结果证实了理论的有效性并展示了DEM算法的鲁棒性,这项工作对于高精度ADC设计的性能评估具有重要参考意义。

Abstract

The inherent capacitor mismatch resulting from process variations is a significant impediment in the designing of high-resolution Analog-to-Digital Converters. Various calibration methods have been previously introduced, often employing additional circuits or external controllers, albeit at the expense of increased silicon area or intricate operational complexities. In this work, we have established the relationship between capacitor mismatches, output deviation, and Total Harmonic Distortion (THD) in capacitor Digital-to-Analog Converters. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. After that, we propose a new compensation strategy that adopts the Dynamic Element Matching (DEM) technique to conventional cyclic ADCs with minimum hardware cost and implement this compensation scheme in a cyclic-pipelined ADC. We reassess the performance of the proposed ADC based on the formulated theory. Importantly, the measurement results of the cyclic ADC have not only confirmed the validity of our proposed theory but also demonstrated the robust performance of the simplified version of the DEM algorithm. This work is constructive for performance estimation in other high-precision ADC designs.

导出引用

杨翼好, 刘国骜, 于健睿, 等. 数据转换器中电容失配的分析与解决方案[J]. 集成电路与嵌入式系统. 2024, 24(12): 1-11 https://doi.org/10.20193/j.ices2097-4191.2024.0056

YANG Yihao, LIU Guoao, YU Jianrui, et al. An analysis for capacitor mismatches in data converters and its solution[J]. Integrated Circuits and Embedded Systems. 2024, 24(12): 1-11 https://doi.org/10.20193/j.ices2097-4191.2024.0056

中图分类号： TN432 (场效应型)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	HWANG Y H, SONG Y, PARK JE, et al. A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS[C]//2018 IEEE Asian Solid-State Circuits Conference (ASSCC),2018:247-248. 本文引用 [1]

[2]	CHEN G, LU W, YOU Y, et al. A 16-bit 8-channel Sigma-Delta ADC for Harmonics Detection System in Power Network[C]//2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),2018: 1-3. 本文引用 [1]

[3]	AMANDEEP K, KARTHIK M B, MUKUL S. A CMOS Image Sensor with Column-Parallel Cyclic-SAR ADC[C]//2020 IEEE International Symposium on Circuits and Systems (ISCAS),2020:1-5. 本文引用 [2]

[4]	DYER K C, KEANE J P, LEWIS S H. Calibration and Dynamic Matching in Data Converters:Part 1: Linearity Calibration and Dynamic-Matching Techniques[J]. IEEE Solid-State Circuits Magazine, 2018, 10(2):46-55. 本文引用 [1]

[5]	WANG X, LI F, WANG Z. A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2020, 67(12):2838-2842. 本文引用 [1]

[6]	CHEN C, SUN J, WANG C, et al. A 10-b 500MS/s Partially Loop-unrolled SAR ADC with a Comparator Offset Calibration Technique[C]//2021 IEEE International Symposium on Circuits and Systems (ISCAS).IEEE,2021. 本文引用 [1]

[7]	HUANG J, MERCIER P P. A 94.2-dB SNDR 142.6-μW VCO-Based Audio ADC with a Split-ADC Differential Pulse Code Modulation Architecture[J]. IEEE Solid-State Circuits Letters, 2021(4):121-124. 本文引用 [1]

[8]	LI H, MADDOX M, COIN M C W, et al. A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL[C]//2018 IEEE International Solid - State Circuits Conference-(ISSCC).IEEE,2018. 本文引用 [1]

[9]	LYU Y, HU Y. A Universal Evaluation Method of Element Matching Strategies for Data Converters Based on Optimal Combination Algorithms[J]. IEEE Transactions on Circuits and Systems I:Regular Papers,2021:1-11. 本文引用 [1]

[10]	NAZVANOV A A, YENUCHENKO M S. A 10-bit Current-steering Fibonacci DAC with DEM[C]//2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus),2019:780-783. 本文引用 [1]

[11]	HSU C W, CHANG S J, HUANG C P, et al. A 12-b 40-MS/s Calibration-Free SAR ADC[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2018, 65(3):881-890. 本文引用 [1]

[12]	SCHREIER R, ZHANG B. Noise-shaped multibit D/A convertor employing unit elements[J]. Electronics Letters, 1995,31:1712-1713. 本文引用 [2]

[13]	REDMAN-WHITE W, BOURNER D J L. Improved dynamic linearity in multi-level Sigma - Delta converters by spectral dispersion of D/A distortion products[C]//1989 European Conference on Circuit Theory and Design,1989:205-208. 本文引用 [3]

[14]	NYS O J A P, HENDERSON R K. An analysis of dynamic element matching techniques in sigma-delta modulation[C]//1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems (ISCAS) IEEE,1996. 本文引用 [3]

[15]	WELZ J, GALTON I, FOGLEMAN E. Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters[J]. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, 2001, 48(11). 本文引用 [3]

[16]	SHU Y S, KUO L T, LO T Y. An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(12). 本文引用 [1]

[17]	LIU J, HSU C K, TANG X, et al. Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2019, 66(4):1342-1354. 本文引用 [1]

[18]	HASEBE K, ETOU S, MIYAZAKI D, et al. A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques[C]//2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),2022:56-57. 本文引用 [1]

[19]	CHAN K L, GALTON I. A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching[C]//2006 IEEE International Solid - State Circuits Conference - (ISSCC),2006:2390-2399. 本文引用 [1]

[20]	NGUYEN K, BANDYOPADHYAY A, ADAMS B, et al. A 108 dB SNR,1.1 mW Oversampling Audio DAC With A Three-level DEM Technique[J]. IEEE Journal of Solid-State Circuits, 2008, 43(12):2592-2600. 本文引用 [1]

[21]	YANG Y, LYU Y, HU Y. A Mismatch Compensation Scheme for Cyclic-pipelined ADC via Dynamic Element Matching Technique[C]//2022 IEEE International Symposium on Circuits and Systems (ISCAS),2022:3229-3233. 本文引用 [1]

[22]	XIE L, LI Z, FENG J, et al. Design and Implementation of a Low-Power Cyclic ADC for X-Ray Detector Readout Circuit[C]//2020 IEEE 20th International Conference on Communication Technology (ICCT).IEEE,2020. 本文引用 [1]

[23]	FUJIMORI I, SUGIMOTO T. A 1.5 V,4.1 mW dual-channel audio delta-sigma D/A converter[J]. IEEE Journal of Solid-State Circuits, 1998, 33(12):1863-1870. 本文引用 [1]

[24]	SHUI T, SCHREIER R, HUDSON F. Mismatch shaping for a current-mode multibit delta-sigma DAC[J]. IEEE Journal of Solid-State Circuits, 1999, 34(3):331-338. 本文引用 [1]

[25]	GALTON I. Spectral shaping of circuit errors in digital-to-analog converters[J]. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, 1997, 44(10):808-817. 本文引用 [1]

[26]	TANG X, SHEN L, KASAP B, et al. An Energy-Efficient Comparator with Dynamic Floating Inverter Amplifier[J]. IEEE Journal of Solid-State Circuits, 2020, 55(4):1011-1022. 本文引用 [1]