为实现高并行计算,全同态加密硬件加速系统需要例化大量密码学原语操作单元。模乘作为全同态加密中最重要的原语操作,其电路实现面积对加速系统面积有较大影响。针对现有模乘器设计中资源使用较多、支持参数范围较小和依赖硬核IP等问题,本文设计了一种基于FPGA的高效蒙哥马利模乘器。该模乘器在算法层面通过NTT-Friendly模数特性、压缩和编码等方法降低计算量,在电路层面通过分时复用和数据整合等方法减少资源。此外,该模乘器支持参数配置以实现不同位宽的蒙哥马利模乘。实验结果表明,本文设计的蒙哥马利模乘器在位宽为32比特时,时钟频率223 MHz,延迟26.9 ns,LUT使用1 313个,FF使用213个,相较于对比对象,资源平均减少32%,延迟平均提高16%,但结构更灵活,具有较强的适用性。

To achieve high parallel computing, fully homomorphic encryption hardware acceleration systems require the instantiation of a large number of cryptographic primitive operation units. As the most crucial primitive operation in fully homomorphic encryption, the circuit implementation area of modular multiplication significant impacts the overall area of the acceleration system. Addressing issues such as excessive resource usage, limited parameter, and dependency on macro core IPs in existing modular multiplier designs, this paper presents an efficient Montgomery modular multiplier based on FPGA. At the algorithmic level, the multiplier reduces the computational load through techniques such as NTT-Friendly modulus characteristics, compression, and encoding. At the circuit level, it minimizes resource through methods like time-division and data integration. Furthermore, the multiplier supports parameter configuration to implement Montgomery modular multiplication for different widths. Experimental results demonstrate that, for a 32-bit width, the designed Montgomery modular multiplier operates at a clock frequency of 223 MHz with a latency of 26.9 ns, utilizing 1 313 LUTs and 213 FFs. Compared to the baseline, the resource consumption is reduced by 32% on average, while the latency is improved by 16% on average, making the design more flexible and highly applicable.