随着信息技术和人工智能的快速发展,物联网终端设备的功能愈加复杂,因其硬件资源受限,导致系统安全面临严重威胁。鉴于此,利用采样寄存器的时序违例行为特性,结合FPGA中DSP IP核内部组合逻辑延迟特征,提出一种基于DSP IP核的双模态可配置软PUF设计方案。首先,分析Xilinx Artix-7 FPGA中的DSP IP核内部结构,根据其组合逻辑延时信息和时序约束,确定正常传输数据的时钟周期范围。然后,根据激励位数需求配置两种不同运算模式,分别施加超频时钟,使采样寄存器在发生时序违例后产生异常运算结果。最后,通过哈希算法和奇偶校验将不同位数的异常数据压缩为1位PUF响应。该方案无需额外设计偏差提取电路,可在不改变硬件结构的条件下灵活配置两种不同激励位数的软PUF实现方式。测试结果表明,两种运算模式的可靠性均超过98%,具备良好的唯一性及抗机器学习攻击能力,验证了其在安全性与实用性方面的可行性与优势。

With the rapid advancement of information technology and artificial intelligence, the increasingly complex functions of IoT terminal devices have resulted in significant security threats due to their limited hardware resources. To address this, this paper proposes a dual-mode configurable software PUF (Physical Unclonable Function) design based on the DSP IP core. This approach leverages the timing violation behavior characteristics of sampling registers and the combinational logic delay features within the DSP IP core of FPGA. First, the internal structure of DSP IP cores in Xilinx Artix-7 FPGA is analyzed, determining the clock cycle range for normal data transmission based on their combinational logic delay information and timing constraints. Next, two distinct operational modes are configured based on the required challenge bit length, with overclocked clocks applied to induce abnormal computational results through timing violation in the sampling registers. Finally, a hash algorithm and parity check are used to compress the abnormal data of varying bit lengths into a 1-bit PUF response. This design eliminates the need for additional bias extraction circuits and allows for flexible configuration of two different challenge bit lengths for the software PUF implementation without modifying the hardware structure. The experimental results demonstrate that both operational modes achieve a reliability of over 98%, with excellent uniqueness and resistance to machine learning attacks, thereby validating the proposed scheme's feasibility and advantages in terms of both security and practicality.