新型电力系统实时仿真对CPU-FPGA异构与多FPGA分布式计算提出了更高要求,通信效率将成为瓶颈问题之一。面对千兆以太网带宽与实时性短板逐渐凸显的现状,提出了一种基于FPGA的万兆以太网高带宽低延迟接口的轻量化设计。物理层基于高速收发器构建,实现低延迟与高可靠性。UDP协议栈采用交替缓存与优先级队列机制,提高数据吞吐并均衡瞬时负载。板级测试结果表明,该设计硬件资源占用率低,最大传输带宽可达9.70 Gb/s,平均传输延迟为0.45 μs,各协议层交互稳定无冲突,为电力系统仿真等应用提供了高效的底层通信支持。

The real-time simulation of new power system puts forward higher requirements for CPU-FPGA heterogeneous computing and multi-FPGA distributed computing, in which communication efficiency may become one of the bottlenecks. Given the current limitations of Gigabit Ethernet in bandwidth and real-time performance, this paper proposes an FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface. PHY is built based on the GT to achieve low latency and high reliability. In the UDP stack, alternating caching and queuing with priority are adopted to improve data throughput and balance instantaneous load. The on-board test results show that the design achieves low hardware resource consumption, a maximum transmission bandwidth of 9.70 Gb/s, an average transmission delay of 0.45 μs and stable interactions between protocol layers without interference, which provides efficient communication support for the simulation of power system and other applications.