针对目前FPGA配置比特流解密认证资源开销大、效率低等问题,基于有限域GF(2³²)乘法运算提出了GMAC_GF32认证算法,并结合CTR模式的AES加密运算设计并实现了一种高效、高安全的FPGA配置比特流解密认证方法。该方法采用四级流水线设计实现AES256_CTR解密模块电路,使得每次解密时间与传输128位数据时间相匹配,最大化提高了FPGA解密的吞吐率,另外,每级流水线运算通过采用4个S-Box并行运算能够提高能量侧信道安全性。认证模块电路通过有限域GF(2³²)运算将现有验证码改进为32位,能够有效降低串行计算验证码的效率,提高时钟利用率,并且通过在认证模块电路引入内置多项式函数能够提高验证码的安全性,防止攻击码流的载入。基于FPGA原型验证板的实验验证结果表明,采用的流水线解密方式提升AES256_CTR算法的解密效率,将解密过程压缩到4个时钟周期;所提认证方法能够在维持认证强度的同时,大幅减少额外认证数据量及隐性时间成本,实现认证算法所消耗的面积资源减少96.5%;最终使得解密认证电路面积没有明显增加。本文提出的方法适用于对性能与安全均有较高要求的FPGA芯片设计场景。

To address the current issues of high resource overhead and low efficiency in FPGA configuration bitstream decryption and authentication, this paper proposes the GMAC_GF32 authentication algorithm based on finite field GF(2³²) multiplication operations. Combined with AES encryption in CTR mode, we design and implement an efficient and highly secure FPGA configuration bitstream decryption and authentication method. The method employs a four-stage pipeline design for the AES256_CTR decryption module, ensuring that each decryption cycle aligns with the time required to transmit 128 bits of data, thereby maximizing the decryption throughput of the FPGA. Additionally, each pipeline stage enhances power side-channel security by utilizingsixteen S-Boxes operating in parallel. The authentication module improves existing verification codes to 32 bits through GF(2³²) operations, effectively mitigating the inefficiency of serial verification code computation, improving clock utilization. The authentication module enhances security by incorporating built-in polynomial functions to prevent the loading of malicious code streams. Experimental validation on an FPGA prototype board demonstrates that the proposed pipeline decryption approach optimizes the AES256_CTR algorithm, compressing the decryption process to four clock cycles. The authentication method significantly reduces additional authentication data volume and hidden time costs while maintaining security strength, achieving a 96.5% reduction in area resource consumption for the authentication algorithm;thereby achieving no noticeable increase in the overall decryption-authentication circuit area. The proposed method is well-suited for FPGA chip design scenarios requiring high performance and robust security.