面向模拟SRAM存算一体芯片的数字接口设计

孔鹤霖; 魏知行; 陈挺然; 潘彪

doi:10.20193/j.ices2097-4191.2025.0030

PDF(10075 KB)

集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (7) : 1-8. DOI: 10.20193/j.ices2097-4191.2025.0030

封面文章

面向模拟SRAM存算一体芯片的数字接口设计

作者信息 +

Digital interface design for analog SRAM memory computing integrated chip

Author information +

文章历史 +

摘要

针对模拟存算一体芯片设计中仿真验证难题,提出一种创新的数字接口设计方案,旨在提高大规模计算场景下的仿真效率。该方案分析SRAM存算一体原理,将SPICE模型与数字控制电路结合,利用数字方法完成模拟存算一体设计的仿真验证,从而提升开发效率。为验证方案的有效性,构建评估体系,对比数字接口仿真与传统模拟电路仿真。结果显示,新方案仿真速度提升2倍以上,配置效率提升1 000倍以上,优势显著。该研究获得科技部重点研发计划 (2021YFB3601300)支持,已在180 nm工艺节点完成流片验证,证实了数字接口设计方案在大规模计算场景下仿真存算一体设计的效率优势。

Abstract

Neural network models demand high processor performance and energy efficiency. The memory-computing integrated architecture is an energy-efficient solution. This paper introduces a digital interface simulation scheme to address simulation verification challenges in analog memory-computing integrated designs and improve simulation efficiency in large-scale computing scenarios. The scheme analyzes SRAM-based memory-computing integration and combines the SPICE model with a digital control circuit. This enables the use of digital methods for simulation and verification, potentially boosting development efficiency. An evaluation system comparing the digital interface simulation with traditional analog circuit simulation reveals that the new solution increases simulation speed by more than 2 times and configuration efficiency by more than 1 000 times. This research is supported by the key research and development program of the ministry of science and technology (2021YFB3601300), and this research has been validated with tape-out at the 180 nm process node, demonstrating the efficiency advantages of the digital interface simulation scheme for memory-computing integrated design in large-scale computing.

导出引用

孔鹤霖, 魏知行, 陈挺然, 等. 面向模拟SRAM存算一体芯片的数字接口设计[J]. 集成电路与嵌入式系统. 2025, 25(7): 1-8 https://doi.org/10.20193/j.ices2097-4191.2025.0030

KONG Helin, WEI Zhixing, CHEN Tingran, et al. Digital interface design for analog SRAM memory computing integrated chip[J]. Integrated Circuits and Embedded Systems. 2025, 25(7): 1-8 https://doi.org/10.20193/j.ices2097-4191.2025.0030

中图分类号： TN4 (微电子学、集成电路(IC))

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	M AZIDAN, J P STRACHAN, W D LU. The future of electronics based on memristive systems[J]. Nature electronics, 2018, 1(1):22-29. 本文引用 [1]

[2]	XUE C, CHANG M. Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices[C]// 2019 International SoC Design Conference (ISOCC), 2019:164-165. 本文引用 [1]

[3]	C JJHANG, C X XUE, J M HUNG, et al. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2021, 68(5):1773-1786. 本文引用 [2]

[4]	DONG Q, SINANGIL M E, ERBAGCI B. A 351TOPS/W and 372.4GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications[C]// 2020 IEEE International Solid-State Circuits Conference, 2020:242-247. 本文引用 [1]

[5]	WANG J C, WANG X W, ECKERT C, et al. A compute SRAM with bit-serial integer/floating-point operations for programmable in-memory vector acceleration[C]// 2019 IEEE International Solid-State Circuits Conference, 2019:224-226. 本文引用 [1]

[6]	WANG J, WANG X, ECKERT C, et al. A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing[J]. IEEE Journal of Solid-State Circuits, 2020(1).DOI:10.1109/jssc.2019.2939682. 本文引用 [1]

[7]	Y D CHIH. 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications[C]// 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021:252-254. 本文引用 [1]

[8]	ZHANG J, WANG Z, VERMA N. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array[J]. IEEE Journal of Solid-State Circuits, 2017, 52(4):915-924. 本文引用 [1]

[9]	A AGRAWAL, A JAISWAL, C LEE, et al. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2018, 65(12):4219-4232. 本文引用 [1]

[10]	Z JIANG, S YIN, J S SEO, et al. C3SRAM:In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing[J]. IEEE Solid-State Circuits Letters, 2019, 2(9):131-134. 本文引用 [1]

[11]	JIANG H W, PENG X C, HUANG S S, et al. CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training[C]// 2019 Proceedings of the International Symposium on Memory Systems, 2019:490-496. 本文引用 [1]

[12]	YU S, JIANG H, HUANG S, et al. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects[J]. IEEE Circuits and Systems Magazine, 2021, 21(3):31-56. 本文引用 [1]

[13]	M E SINANGIL. A 7nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS[J]. IEEE Journal of Solid-State Circuits, 2021, 56(1):188-198. 本文引用 [1]