高效Winograd卷积硬件设计及其量化方案

严峥; 张宸硕; 白一川; 杜源; 杜力

doi:10.20193/j.ices2097-4191.2025.0042

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集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (8) : 41-52. DOI: 10.20193/j.ices2097-4191.2025.0042

新兴计算芯片设计研究专刊

高效Winograd卷积硬件设计及其量化方案

作者信息 +

Design of efficient Winograd convolution hardware and its quantization scheme

Author information +

文章历史 +

摘要

卷积是CNN网络中常见的运算,卷积中的乘累加运算功耗较高,限制了许多CNN硬件加速器的性能,减少卷积的乘法次数是提高CNN加速器性能的有效途径之一。作为一种快速卷积算法,Winograd算法可以减少卷积中高达75%的乘法。然而,Winograd卷积中的权重分布显著不同,导致为了保持相似的精度需要更长的量化位宽,从而抵消了因减少乘法次数带来的硬件优化效果。针对这一问题进行定量分析,提出了一种新的Winograd卷积量化方案,实现了小于1%的精度损失。为了进一步降低硬件成本,将近似乘法器应用于Winograd卷积。与传统卷积计算块相比,Winograd计算块节省了27.3%的面积,近似乘法器在Winograd计算块中应用节省了39.6%的面积,且性能损失不明显。

Abstract

Convolution is the most common operation in CNN networks, and the power consumption of multiplication and accumulation operations in convolution is high, which limits the performance of many CNN hardware accelerators. Reducing the number of multiplications in convolution is one of the effective ways to improve the performance of CNN accelerators. As a fast convolution algorithm, Winograd algorithm could reduce up to 75% multiplications in convolution. However, the weights of the model for Winograd convolution have a significantly different distribution, which results in longer quantization bit width to maintain similar accuracy and neutralizes the hardware reduction brought by the reduction of multiplications. In this paper, we analyze this problem quantitively and propose a new quantization scheme for Winograd convolution. The quantized Winograd computation hardware module is implemented with accuracy loss less than 1%. To further reduce the hardware cost, we apply the approximate multiplier (AM) to Winograd convolution. Compared with the conventional convolution computation block, the Winograd block saves 27.3% of the area, and the application of the approximate multiplier in Winograd block saves 39.6% of the area without significant performance loss.

导出引用

严峥, 张宸硕, 白一川, 等. 高效Winograd卷积硬件设计及其量化方案[J]. 集成电路与嵌入式系统. 2025, 25(8): 41-52 https://doi.org/10.20193/j.ices2097-4191.2025.0042

YAN Zheng, ZHANG Chenshuo, BAI Yichuan, et al. Design of efficient Winograd convolution hardware and its quantization scheme[J]. Integrated Circuits and Embedded Systems. 2025, 25(8): 41-52 https://doi.org/10.20193/j.ices2097-4191.2025.0042

中图分类号： TN492 (专用集成电路)

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