低温存内计算芯片设计研究综述

束宇豪; 李怡霏; 王禁城; 刘伟强; 哈亚军

doi:10.20193/j.ices2097-4191.2025.0046

PDF(3764 KB)

集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (8) : 23-30. DOI: 10.20193/j.ices2097-4191.2025.0046

新兴计算芯片设计研究专刊

低温存内计算芯片设计研究综述

束宇豪 ¹ ,
李怡霏 ² ,
王禁城 ² ,
刘伟强 ¹ ,
哈亚军 ²^,^*

作者信息 +

Review on cryogenic in-memory computing chip design

SHU Yuhao ¹ ,
LI Yifei ² ,
WANG Jincheng ² ,
LIU Weiqiang ¹ ,
HA Yajun ²^,^*

Author information +

文章历史 +

摘要

随着人工智能、量子计算等前沿技术的快速发展,对高性能计算芯片的需求不断提升。然而,传统冯·诺依曼架构受限于存储墙和功耗墙等因素,已难以满足数据密集型计算应用的算力需求。低温存内计算结合了低温CMOS器件的优异电学特性与存内计算架构的高带宽、低延迟优势,为突破算力瓶颈提供了一种新的解决方案。综述了低温环境下CMOS器件及多种存储介质的关键特性,系统梳理了低温存内计算在人工智能与量子计算领域的典型架构、关键实现及性能表现,并分析了其在器件工艺、电路系统、EDA工具等层面的挑战及未来发展趋势。

Abstract

With the rapid advancement of cutting-edge technologies such as artificial intelligence and quantum computing, the demand for high-performance computing chips continues to increase. However, traditional von Neumann architectures are increasingly constrained by the memory wall and power wall, making it difficult to meet the computing demands of data-intensive applications. Cryogenic in-memory computing combines the superior electrical properties of cryogenic CMOS devices with the high bandwidth and low latency advantages of in-memory computing architectures, providing a new solution to overcome computing bottlenecks. This review summarizes the key characteristics of CMOS devices and various memory media at cryogenic temperatures, systematically reviews representative architectures, key implementations, and performance metrics of cryogenic in-memory computing in the fields of artificial intelligence and quantum computing. Moreover, this review analyzes the challenges and development trends at the levels of device technology, circuit systems, and EDA tools.

导出引用

束宇豪, 李怡霏, 王禁城, 等. 低温存内计算芯片设计研究综述[J]. 集成电路与嵌入式系统. 2025, 25(8): 23-30 https://doi.org/10.20193/j.ices2097-4191.2025.0046

SHU Yuhao, LI Yifei, WANG Jincheng, et al. Review on cryogenic in-memory computing chip design[J]. Integrated Circuits and Embedded Systems. 2025, 25(8): 23-30 https://doi.org/10.20193/j.ices2097-4191.2025.0046

中图分类号： TN492 (专用集成电路)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	RESCH S, CILASUN H, KARPUZCU U R. Cryogenic PIM: Challenges & Opportunities[J]. IEEE Computer Architecture Letters, 2021, 20(1):74-77. 本文引用 [3]

[2]	ZOTA C, FERRARIS A, CHA E, et al. Energy-efficient computing at cryogenic temperatures[J]. Nature Electronics, 2024:1-9. 本文引用 [4]

[3]	程然, 李博, 王宗巍, 等. 面向高性能计算的低温芯片技术:发展和挑战[J]. 中国科学:信息科学, 2024, 54(1):88-101. CHENG R, LI B, WANG Z W, et al. Low-temperature chip technology for high-performance computing: development and challenges[J]. Science in China:Information Sciences, 2024, 54(1):88-101 (in Chinese). 本文引用 [4]

[4]

SEBASTIAN

, LE

GALLO M

, KHADDAM-ALJAMEH

, et al. Memory devices and applications for in-memory computing[J]. Nature Nanotechnology, 2020, 15(7):529-544.

https://doi.org/10.1038/s41565-020-0655-z

https://www.ncbi.nlm.nih.gov/pubmed/32231270

本文引用 [2] 摘要

Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing.

[5]	SHU Y, NING B, LI Y, et al. Overview of Cryogenic CMOS Based Computing Systems[J]. Integrated Circuits and Systems, 2024, 1(4):167-177. 本文引用 [5]

[6]	ZHANG Y, LU T, WANG W, et al. Characterization and Modeling of Native MOSFETs Down to 4.2 K[J]. IEEE Transactions on Electron Devices, 2021, 68(9):4267-4273. 本文引用 [5]

[7]	SHAMIEH L A, WANG W-C, ZHANG S, et al. Cryogenic Operation of Computing-In-Memory based Spiking Neural Network[C]// Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design. New York,NY,USA: Association for Computing Machinery, 2024:1-6. 本文引用 [5]

[8]	WANG P, PENG X, CHAKRABORTY W, et al. Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator[C]// 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021. 本文引用 [5]

[9]	WANG W-C, SALIGRAM R, SHARMA S, et al. Cool-CIM: Cryogenic Operation of Analog Compute-In-Memory for Improved Power-efficiency[C]// 2023 International Electron Devices Meeting (IEDM), 2023. 本文引用 [5]

[10]	SHU Y, ZHANG H, DENG Q, et al. eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11):3827-3839. 本文引用 [8]

[11]	SHU Y, ZHANG H, DENG Q, et al. CIMC:A 603 TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing[C]// 2023 IEEE Custom Integrated Circuits Conference (CICC), 2023. 本文引用 [4]

[12]	SINGH PARIHAR S, KUMAR S, CHATTERJEE S, et al. Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM[J]. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2025, 11:34-41. 本文引用 [10]

[13]	ALAM S, HUTCHINS J, HOSSAIN M S, et al. Cryogenic In-Memory Matrix-Vector Multiplication using Ferroelectric Superconducting Quantum Interference Device (FE-SQUID)[C]// 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023. 本文引用 [7]

[14]	LIU Y, LEE A, QIAN K, et al. Cryogenic in-memory computing using magnetic topological insulators[J]. Nature Materials, 2025:1-6. 本文引用 [9]

[15]	WANG P, PENG X, CHAKRABORTY W, et al. Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction[C]// 2020 IEEE International Electron Devices Meeting (IEDM). San Francisco,CA,USA: IEEE, 2020:38.5.1-38.5.4. 本文引用 [4]

[16]	KANG D S, YU S. Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter[J]. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022, 8(2):128-133. 本文引用 [4]

[17]	QIAN K, LEE A, XIAO Z, et al. Cryogenic In-Memory Computing Circuits with Giant Anomalous Hall Current in Magnetic Topological Insulators for Quantum Control[C]// 2024 IEEE International Electron Devices Meeting (IEDM), 2024. 本文引用 [5]

[18]	ALAM S, ISLAM M M, HOSSAIN M S, et al. CryoCiM: Cryogenic compute-in-memory based on the quantum anomalous Hall effect[J]. Applied Physics Letters, 2022, 120(14). 本文引用 [2]

[19]	HOU Y, GE W, GUO Y, et al. Cryogenic In-MRAM Computing[C]// 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021. 本文引用 [6]

[20]	HOU Y, LIU-SUN C, LIU B, et al. BIST-Supported Cryogenic Write Trimming with In-MRAM Computing Case Study[J]. IEEE Transactions on Nanotechnology, 2023, 22:126-135. 本文引用 [3]

[21]	PARIHAR S S, THOMANN S, PAHWA G, et al. Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5 nm FinFETs[J]. IEEE Open Journal of Circuits and Systems, 2023, 4:258-270. 本文引用 [2]

[22]	CHIANG H-L, WU J-J, CHOU C-H, et al. Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies[C]// 2021 IEEE International Electron Devices Meeting (IEDM), 2021. 本文引用 [1]

[23]	WANG Z, TANG Z, GUO A, et al. Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs[J]. IEEE Electron Device Letters, 2020, 41(5):661-664. 本文引用 [1]

[24]	SUN Y, GU Y, XU K, et al. A Universal Temperature-Dependent Carrier Backscattering Model for Low-Temperature High-Performance CMOS Applications[J]. IEEE Transactions on Electron Devices, 2024, 71(1):107-113. 本文引用 [1]

[25]	HAN H-C, JAZAERI F, D’AMICO A, et al. Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing[C]// ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021. 本文引用 [1]