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超维计算硬件设计:进展、趋势和展望
Hyperdimensional computing hardware: progress, trends and prospects
超维计算是一种受人脑启发的新兴计算范式,其具有低复杂度、强鲁棒性、强可解释性等优势,在边缘侧应用中具有广阔的应用前景。超维计算通过模拟人脑的信息处理机制,利用超维向量和简单逻辑运算实现复杂认知功能,以轻量级的编码-查询流程替代神经网络的多层复杂结构,为高能效边缘侧人工智能芯片提供了新的技术路径。文中系统地阐述了超维计算的理论基础与算法演进,并探讨了使用硬件加速其中各个步骤的可行性。在此基础之上,对聚焦于查询步骤的专用硬件进行详细介绍,归纳出FPGA、ASIC、存内计算这三类实现方式,并分析了不同方式的优势和劣势。此外,针对现有超维查询硬件的共同不足,介绍一些最新的研究进展。最后,提出现有超维计算硬件面临的挑战,并对未来研究方向进行了展望。
Hyperdimensional computing (HDC), an emerging computing paradigm drawing inspiration from the human brain, boasts several notable advantages, including low complexity, exceptional robustness, and high interpretability. Consequently, it holds immense potential for a wide array of applications in edge-side applications. HDC serves as an innovative approach that mimics the human brain's information processing mechanisms. By leveraging hyperdimensional vectors and straightforward logical operations, it can accomplish complex cognitive functions. Instead of relying on the complicated architecture of neural network with multi-layers, it employs a lightweight encoding-querying process, paving a fresh technical avenue for the development of highly efficient edge-side artificial intelligence chips. This review provides a meticulous and in-depth analysis of the theoretical foundations and the progressive development of algorithms within HDC, and thoroughly investigates the viability of implementing hardware acceleration techniques at every step of HDC. Based on this, this review focuses on the dedicated hardware for the querying step, summarizes the three implementation methods of FPGA, ASIC, and in-memory computing, and analyzes the advantages and disadvantages of different methods. Moreover, considering the prevalent shortcomings inherent in existing hardware for hyperdimensional querying, this review presents some most recent research advancements. Finally, the challenges confronting hardware for HDC are delineated, and the promising avenues for its future research endeavors are outlined.
超维计算 / FPGA / ASIC / 超维关联存储器 / 存内计算
hyperdimensional computing / FPGA / ASIC / hyperdimensional associative memory / CiM
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Codifying memories is one of the fundamental problems of modern Neuroscience. The functional mechanisms behind this phenomenon remain largely unknown. Experimental evidence suggests that some of the memory functions are performed by stratified brain structures such as the hippocampus. In this particular case, single neurons in the CA1 region receive a highly multidimensional input from the CA3 area, which is a hub for information processing. We thus assess the implication of the abundance of neuronal signalling routes converging onto single cells on the information processing. We show that single neurons can selectively detect and learn arbitrary information items, given that they operate in high dimensions. The argument is based on stochastic separation theorems and the concentration of measure phenomena. We demonstrate that a simple enough functional neuronal model is capable of explaining: (i) the extreme selectivity of single neurons to the information content, (ii) simultaneous separation of several uncorrelated stimuli or informational items from a large set, and (iii) dynamic learning of new items by associating them with already "known" ones. These results constitute a basis for organization of complex memories in ensembles of single neurons. Moreover, they show that no a priori assumptions on the structural organization of neuronal ensembles are necessary for explaining basic concepts of static and dynamic memories.
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刘文波, 姚翼荣, 张弓, 等. 超维计算概念、应用及研究进展[J]. 系统工程与电子技术, 2023, 45(7):1938-1956.
超维计算是一种受大脑工作机制启发的新兴认知模型, 使用信息的高维、随机、全息分布式表示作为处理对象, 具有低运算成本、快速学习过程、高硬件友好性、强鲁棒性、不依赖大数据和优异的模型可解释性等优势, 在分类识别、信号处理、多任务学习、信息融合、智能决策等领域有着良好的应用前景。近年来, 超维计算受到的关注量持续增加, 展现出巨大的发展潜力, 为研究人员提供了一种新选择。本文详细介绍了超维计算的发展历史、基本原理和模型框架, 给出超维计算的典型应用实例, 并对超维计算现阶段存在的问题和未来可能的发展方向进行了探讨。
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Hyperdimensional computing (HDC) is a brain-inspired computational framework that relies on long hypervectors (HVs) for learning. In HDC, computational operations consist of simple manipulations of hypervectors and can be incredibly memory-intensive. In-memory computing (IMC) can greatly improve the efficiency of HDC by reducing data movement in the system. Most existing IMC implementations of HDC are limited to binary precision which inhibits the ability to match software-equivalent accuracies. Moreover, memory arrays used in IMC are restricted in size and cannot immediately support the direct associative search of large binary HVs (a ubiquitous operation, often over 10,000+ dimensions) required to achieve acceptable accuracies. We present a multi-bit IMC system for HDC using ferroelectric field-effect transistors (FeFETs) that simultaneously achieves software-equivalent-accuracies, reduces the dimensionality of the HDC system, and improves energy consumption by 826x and latency by 30x when compared to a GPU baseline. Furthermore, for the first time, we experimentally demonstrate multi-bit, array-level content-addressable memory (CAM) operations with FeFETs. We also present a scalable and efficient architecture based on CAMs which supports the associative search of large HVs. Furthermore, we study the effects of device, circuit, and architectural-level non-idealities on application-level accuracy with HDC.© 2022. The Author(s).
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