基于AST与DPI实现算法加速器的敏捷验证平台

李亚伟; 谢昕洋; 孙逸睿; 赵双妹; 苏国彬

doi:10.20193/j.ices2097-4191.2025.0062

PDF(16963 KB)

集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (12) : 18-26. DOI: 10.20193/j.ices2097-4191.2025.0062

智能嵌入式系统软硬件协同设计与应用专栏

基于AST与DPI实现算法加速器的敏捷验证平台

李亚伟 ¹ ,
谢昕洋 ¹^,² ,
孙逸睿 ¹^,² ,
赵双妹 ¹ ,
苏国彬 ¹^,^*

作者信息 +

Design of agile verification platform for algorithmic accelerator based on AST and DPI

LI Yawei ¹ ,
XIE Xinyang ¹^,² ,
SUN Yirui ¹^,² ,
ZHAO Shuangmei ¹ ,
SU Guobin ¹^,^*

Author information +

文章历史 +

摘要

针对算法加速器模型与RTL抽象层次不一致、验证环境构建复杂和跨工具链与多语言协同等问题,设计并实现了基于AST与DPI的算法加速器敏捷验证平台。使用AST解析算法模型C程序的语法树结构,将特定算法函数映射为SV DPI接口生成UVM参考模型和直接测试向量,自动化解析RTL代码生成基于UVM的验证环境,并通过生成的DPI接口将参考模型与真实输出进行比较以验证功能正确性。该平台有效降低了验证人员的算法加速器验证门槛,通过一套自动化工具可直接生成工业产出可用的验证环境,极大缩短了验证周期。

Abstract

To address the issues of inconsistent abstraction levels in algorithm accelerator models, complex verification environment construction, and cross-toolchain and multi-language collaboration, an agile verification platform for algorithm accelerators based on AST and DPI is designed. Using the AST parsing algorithm model for the syntax tree structure of the C program, specific algorithm functions are mapped to the SV DPI interface to generate UVM reference models and direct test vectors. The RTL code is automatically parsed to generate a UVM-based verification environment, and the reference model is compared with the actual output through the generated DPI interface to verify the function correctness. This platform effectively lowers the verification threshold for algorithm accelerator verification personnel. With automated tools, it can directly create a verification environment aligned with the industrial output, significantly shortening the verification cycle.

导出引用

李亚伟, 谢昕洋, 孙逸睿, 等. 基于AST与DPI实现算法加速器的敏捷验证平台[J]. 集成电路与嵌入式系统. 2025, 25(12): 18-26 https://doi.org/10.20193/j.ices2097-4191.2025.0062

LI Yawei, XIE Xinyang, SUN Yirui, et al. Design of agile verification platform for algorithmic accelerator based on AST and DPI[J]. Integrated Circuits and Embedded Systems. 2025, 25(12): 18-26 https://doi.org/10.20193/j.ices2097-4191.2025.0062

中图分类号： TN47 (大规模集成电路、超大规模集成电路)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	隋金雪, 郁添林, 沈姒清, 等. 基于UVM的可重用硬件加速器验证平台[J]. 计算机仿真, 2023, 40(8):350-354. SUI J X, YU T L, SHEN S Q, et al. Verification Platform of UVM-Based Resuable Hardware Accelerator[J]. Computer Simulation, 2023, 40(8):350-354 (in Chinese). 本文引用 [1]

[2]	杜越, 吴益然, 郑杰良. 基于VIP与SystemVerilog的硬件加速器仿真模型设计[J]. 计算机与网络, 2024, 50(4):307-313. DU Y, WU Y R, ZHENG J L. Design of Hardware Accelerator Simulation Model Based on VIP and SystemVerilog[J]. Computer and Network, 2024, 50(4):307-313 (in Chinese). 本文引用 [1]

[3]	王锋, 王磊, 银磊. SoC芯片UVM平台自动化开发系统[J]. 中国集成电路, 2023, 32(3):72-77. WANG F, WANG L, YIN L. Automatic System of Developing UVM Testbench for SoC[J]. China Integrated Circuit, 2023, 32(3):72-77 (in Chinese). 本文引用 [1]

[4]	刘斌, 虞小鹏, 谭年熊. 面向SoC系统的可扩展UVM自动化验证平台[J]. 电子设计工程, 2024, 32(7):158-163. LIU B, YU X P, TAN N X. Scalable UVM automation verification platform for SoC system[J]. Electronic Design Engineering, 2024, 32(7):158-163 (in Chinese). 本文引用 [1]

[5]	A SABRY. A Novel Approach to Automated UVM Testbench Generation[C]// 2024 International Conference on Microelectronics(ICM),Doha,Qatar, 2024:1-5. 本文引用 [1]

[6]	M V K KALYAN, M VINEETH, S RAJAGOPALAN. Robust Modular UVM Framework for Peripheral Verification[C]// 2024 IEEE 21st India Council International Conference (INDICON),Kharagpur,India, 2024:1-6. 本文引用 [1]

[7]

徐瀅, 傅紫薇, 张伟, 等. 基于抽象语法树嵌入的智能合约漏洞检测技术[J]. 计算机工程, 2025, 51(9):149-157.

https://doi.org/10.19678/j.issn.1000-3428.0069306

摘要

在目前基于深度学习的智能合约漏洞检测方案中，直接使用字节码或源码进行文本序列的特征表达存在对程序语义特征理解不足的问题。基于抽象语法树(AST)嵌入的智能合约漏洞检测技术充分考虑了合约向量化表达需要的语法和语义特征以及合适的处理粒度，能够更加准确地捕捉智能合约漏洞特征。根据Solidity语法树解析设计一种AST嵌入的智能合约向量化方法，对语句级别的节点类型递归划分生成一系列语句树，然后采用递归神经网络自底向上地对每个语句树进行编码，将复杂的AST结构转化为语句级别的特征向量，在此基础上构建基于注意力机制的双向门控循环神经网络(BiGRU-ATT)模型，实现对语句树序列特征的学习，完成对重入漏洞、未校验返回值、时间戳依赖、访问权限控制和拒绝服务攻击5种典型漏洞的检测及分类。实验结果表明，基于AST嵌入的向量化方法相较于直接将源码视为文本序列进行向量化的方法在微观F1值(micro-F1)和宏观F1值(macro-F1)指标上分别提高了13和10百分点，在时间戳依赖、访问权限控制以及拒绝服务攻击漏洞分类任务中，BiGRU-ATT模型的F1值高达88%以上。

, FU

Z W

, ZHANG

, et al. Smart Contract Vulnerability Detection Technology Based on Abstract Syntax Tree Embedding[J]. Computer Engineering, 2025, 51(9):1-8 (in Chinese).

https://doi.org/10.1063/1.31765

https://pubs.aip.org/aip/acp/article/51/1/1-14/567836

本文引用 [1]

[8]	王鑫, 陈博. 基于DPI-C的脉动阵列模块验证平台[J]. 计算机测量与控制, 2023, 31(6):293-298. WANG X, CHEN B. Verification Platform of Systolic Array Module Based on DPI-C[J]. Computer Measurement & Control, 2023, 31(6):293-298 (in Chinese). 本文引用 [1]

[9]

任传宝, 崔建国, 鲁迎春, 等. 应用直接编程接口技术提高片上系统的UVM验证重用性[J]. 微电子学与计算机, 2021, 38(6):20-26,32.

REN

C B

, CUI

J G

, LU

Y C

, et al. Using direct programming interface technology to improve the reusability of UVM verification of system on chip[J]. Microelectromics & Computer, 2021, 38(6):20-26,32 (in Chinese).

本文引用 [1]

[10]	李璐, 周春良, 冯曦, 等. 基于DPI-C接口的可扩展SoC验证平台[J]. 电子设计工程, 2018, 26(4):136-140. LI L, ZHOU C L, FENG X, et al. An extensibleSoC verification platform based on DPI-C interface[J]. Electronic Design Engineering, 2018, 26(4):136-140 (in Chinese). 本文引用 [1]

[11]	郑锐, 沈剑良, 刘冬培, 等. 基于UVM的PCIe交换芯片Switch子系统验证平台的设计[J]. 计算机应用研究, 2025, 42(5):1480-1489. ZHENG R, SHEN J L, LIU D P, et al. Design of verification platform for Switch subsystem of PCIe switching chip based on UVM[J]. Application Research of Computers, 2025, 42(5):1480-1489 (in Chinese). 本文引用 [1]