一种基于VCD表示的CHI协议事务解析验证方法

张剑锋; 邵靖杰; 廖湘龙; 曾聘

doi:10.20193/j.ices2097-4191.2025.0079

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集成电路与嵌入式系统 ›› 2025, Vol. 25 ›› Issue (12) : 66-75. DOI: 10.20193/j.ices2097-4191.2025.0079

研究论文

一种基于VCD表示的CHI协议事务解析验证方法

作者信息 +

A transaction parsing and verification method for CHI protocol based on VCD representation

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摘要

传统硬件验证依赖人工分析波形信号,面临效率低、易出错、事务级行为难以追溯等问题,文中提出一种基于VCD数据和PyVCD库的多核处理器中CHI协议验证的辅助工具,可以提高事务波形分析的效率。VCD(Value Change Dump)是国际标准的Verilog波形数据文件格式,PyVCD是一个开源的纯Python代码库,用于解析VCD文件。通过tcl脚本从各种仿真工具中导出指定信号的波形数据,并将其转换为VCD格式。再使用PyVCD库对波形进行算法分析,实现波形结构化解析与事务重构算法,将分布的Flit数据聚合为完整事务对象序列。获取波形数据并将不同节点不同通道的离散Flit组合为完整的事务。在获得事务对象序列后,将事务对象转换为ASCII字符串,生成字符信号序列并生成VCD文件,用于在波形软件中查看事务级波形,解析协议中事务的性能参数,而且开发了Goldmemory工具,分析系统中多个节点的事务对象序列,自动判断数据错误等场景。基于该方法的平台已在多核处理器工程中部署,通过波形分析CHI事务,大幅提高了仿真验证的效率,同时能够快速定位架构设计的性能瓶颈以实现架构的快速迭代优化。

Abstract

Traditional hardware verification relies on manual analysis of waveform signals, which faces problems such as low efficiency, easy errors, and difficulty in tracing transaction level behavior. Therefore, this paper proposes an auxiliary tool for verifying CHI protocol in multi-core processors based on VCD data and PyVCD library, which can improve the efficiency of transaction waveform analysis. VCD (Value Change Dump) is an international standard Verilog waveform data file format, and PyVCD is an open-source pure Python code library used for parsing VCD files. Our method exports waveform data of specified signals from various simulation tools through TCL scripts and converts it to VCD format. Further use the PyVCD library to perform algorithm analysis on waveforms, implement waveform structured parsing and transaction reconstruction algorithms, and aggregate distributed Flit data into a complete sequence of transaction objects. Obtain waveform data and combine discrete Flits from different nodes and channels into a complete transaction. After obtaining the transaction object sequence, convert the transaction object into an ASCII string, generate a character signal sequence, and create a VCD file for viewing transaction level waveforms in waveform software. Analyze the performance parameters of transactions in the protocol. Developed the Goldmemory tool to analyze the transaction object sequence of multiple nodes in the system and automatically identify data errors and other scenarios. The platform based on this method has been deployed in multi-core processor engineering, and through waveform analysis of CHI transactions, the efficiency of simulation verification has been greatly improved. At the same time, it can quickly locate performance bottlenecks in architecture design to achieve rapid iterative optimization of the architecture.

导出引用

张剑锋, 邵靖杰, 廖湘龙, 等. 一种基于VCD表示的CHI协议事务解析验证方法[J]. 集成电路与嵌入式系统. 2025, 25(12): 66-75 https://doi.org/10.20193/j.ices2097-4191.2025.0079

ZHANG Jianfeng, SHAO Jingjie, LIAO Xianglong, et al. A transaction parsing and verification method for CHI protocol based on VCD representation[J]. Integrated Circuits and Embedded Systems. 2025, 25(12): 66-75 https://doi.org/10.20193/j.ices2097-4191.2025.0079

中图分类号： TP332 (运算器和控制器(CPU})

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	HOROWITZ M, STARK D, ALON E. Digital circuit design trends[J]. IEEE Journal of Solid-State Circuits, 2008, 43(4):757-761. https://doi.org/10.1109/JSSC.2008.917523 http://ieeexplore.ieee.org/document/4476489/ 本文引用 [1]

[2]	HU S S, JI W X, WANG Y Z, et al. Survey on cache coherence protocol and performance optimization for chip multi-processor[J]. Journal of Software, 2017, 28(4):1027-1047. 本文引用 [1]

[3]	JAIN A, DWIVEDI R K, ALSHAZLY H, et al. Design and simulation of ringnetwork-on-chip for different configured nodes[J]. Computers,Materials&Continua, 2022, 71(2):4085-4100. 本文引用 [1]

[4]	ASADI B, ZIA S M, AL-KHAFAJI H M R, et al. Network-on-chip and photonic network-on-chip basic concepts: a survey[J]. Journal of Electronic Testing, 2023, 39(1):11-25. https://doi.org/10.1007/s10836-023-06046-x 本文引用 [1]

[5]	MASDARI M, QASEMS N, PAI H T. Optimizing Network-on-Chip UsingMetaheuristic Algorithms: A Comprehensive Survey[J]. icroprocessors andMicrosystems, 2023:104970. 本文引用 [1]

[6]	裴晓芳, 仇李琦, 张正. 基于 RISC-V的 NoC 配置管理单元设计及验证[J]. 单片机与嵌入式系统应用, 2023, 23(3):12-15,19. PEI X F, QIU L Q. Design and Verification of NoC Configuration Management Unit Based on RISC-V[J]. Microcontrollers and Embedded Systems, 2023, 23(3):12-15,19 (in Chinese). 本文引用 [1]

[7]	BATTEN C, LEE J W. Special Issue on Top Picks From the 2022 Computer Architecture Conferences[J]. IEEE Micro, 2023, 43(4):6-10. 本文引用 [1]

[8]	CHEN C W, HSIA A, ZHAN Y W, et al. Energy-efficient hybrid coherence protocol for multicore processors[J]. Cluster Computing, 2018, 21:1521-1541. https://doi.org/10.1007/s10586-018-1947-z 本文引用 [1]

[9]	马彬, 刘威. SoC 芯片上 AXI总线IP 验证[J]. 电子设计工程, 2023, 31(13):56-60. MA B, LIU W. Verification of AXI Bus IP on SoC Chip[J]. Electronic Design Engineering, 2023, 31(13):56-60 (in Chinese). 本文引用 [1]

[10]	ROSET JULIA M. Extending a modem RISC-V vector accelerator with direct access to the memory hierarchy through AMBA 5 CHI[D]. Barcelona: Universitat Politècnica de Catalunya, 2022. 本文引用 [1]

[11]	ZHENG X, ZENG S, ZHONG Y, et al. An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits[J]. IEEE Embedded Systems Letters, 2024. 本文引用 [1]

[12]	IEEE Std 1364-1995. IEEE Standard Hardware Description Language Based on the VHDL[S]. 1995. 本文引用 [1]

[13]	IEEE Std 1364-2001. IEEE Standard Hardware Description Language Based on the VHDL[S]. 2001. 本文引用 [1]

[14]	Python Package Index. Pyvcd library[EB/OL]. [2025-09]. https://pypi.org/project/pyvcd/. https://pypi.org/project/pyvcd/ 本文引用 [1]

[15]	Python Package Index. vcdparser library[EB/OL]. [2025-09]. https://pypi.org/project/vcdparser/. https://pypi.org/project/vcdparser/ 本文引用 [1]