间接内存访问在图计算、稀疏线性代数等数据密集型应用中广泛存在，其非规则访存模式因时空局部性差导致缓存性能显著下降。传统流式预取器难以有效捕获通过索引数组动态计算目标地址的访问模式（如x[a[i]]）。本文提出动态多模式感知预取器（DMP）以解决这一挑战：DMP采用轻量化移位差分匹配机制，比较索引数据序列与目标地址序列，完成间接访问模式的识别；基于开源玄铁C910 RISC-V处理器的FPGA原型验证表明，DMP使稀疏矩阵向量乘（SpMV）的L1数据缓存缺失率降低27.3%，算法运行时间加速1.07–1.22倍。实验证明DMP在提升间接访存性能的同时，保持了低硬件开销与高可移植性，为现代处理器非规则访存优化提供了实用解决方案。

Indirect memory accesses, prevalent in data-intensive applications like graph processing and sparse linear algebra, exhibit irregular patterns that severely degrade cache performance due to their low spatial/temporal locality. Traditional stride-based prefetchers fail to capture such patterns where target addresses are dynamically computed through index arrays (e.g., x[a[i]]). This paper proposes the dynamic multi-pattern-aware prefetcher (DMP) to address these challenges. DMP introduces a lightweight shifted differential matching mechanism to autonomously identify indirect access patterns by comparing index data sequences with target address sequence. Implemented on the open-source XuanTie C910 RISC-V processor, DMP reduces L1 data cache miss rates by 27.3% and achieves speedups of 1.07–1.22× for Sparse Matrix-Vector Multiplication (SpMV) algorithm. This work provides a hardware-efficient solution for non-contiguous memory access patterns in modern processors.