针对Chiplet互连场景下100Gbps PAM-4有线接收机模拟前端面临的带宽、线性度与集成度三重挑战。本文设计了一种基于跨导-跨阻放大器连续时间线性均衡器的高性能模拟前端，实现对信道的高效均衡补偿。该模拟前端同时也集成了由非对称T-coil、可编程衰减器与AC耦合器组成的宽带输入匹配网络，用以提高系统的线性度。内置的基于跨导-跨阻放大器的两级级联连续时间线性均衡器不仅能够同时实现低频到高频增益的大范围调整，而且具有可变增益放大器的功能。基于28nm CMOS工艺设计的模拟前端，核心面积为0.012mm²，功耗为9.94mW，均衡调节范围达2.25dB~13.39dB。均衡后100Gbps PAM-4输出信号眼高超过100mV，眼宽超过0.52UI。

To tackle the concurrent challenges of bandwidth, linearity, and integration in the analog front-end (AFE) of a 100-Gbps PAM-4 wireline receiver for Chiplet interconnect applications, this paper presents a high-performance AFE architecture based on a transconductance–transimpedance amplifier (GM-TIA) continuous-time linear equalizer (CTLE). The proposed AFE efficiently compensates for channel loss while maintaining high linearity through an integrated broadband input matching network consisting of an asymmetric T-coil, a programmable attenuator, and an AC coupler. A two-stage cascaded GM-TIA-based CTLE enables wide-range gain tuning from low to high frequencies and also serves as a variable-gain amplifier (VGA). Designed in a 28-nm CMOS process, the AFE occupies a core area of 0.012 mm² with the power dissipation of 9.94 mW. The equalization tuning range extends from 2.25 dB to 13.39 dB. After equalization, the 100-Gbps PAM-4 output exhibits an eye height greater than 100 mV and an eye width exceeding 0.52 UI.