DPWM是数字控制开关电源的核心，为解决DPWM高分辨率与系统工作频率的矛盾，本文设计了一种基于FPGA的高分辨率DPWM方案，基于传统计数-比较器结构实现4ns 14bit低分辨率延迟单元，采用进位延迟链实现100ps 7bit高分辨率延迟单元。本文提出的新型混合结构可实现对上升沿和下降沿的高分辨率延迟独立调节，并具有实时自校准单元保证延迟线的调整精度，防止梯度调整跨过低分辨周期造成失调稳定性问题。该架构采用进位延迟链级联设计且PWM通过BUFG全局驱动，可进行自动全局布线，提高了系统移植性。实验表明，该架构的高分辨率延迟单元都在100ps以下，平均延迟为67ps，具有较高的线性度和单调性。

DPWM is the core of digital control switching power supply. To address the conflict between the high resolution of DPWM and the system operating frequency, this paper designs a high-resolution DPWM scheme based on FPGA. A 4ns 14 bit low-resolution delay unit is implemented based on the traditional counter-comparator structure, and a 100ps 7 bit high-resolution delay unit is achieved using a carry delay chain. The novel hybrid structure proposed in this paper can independently adjust the high-resolution delay of the rising and falling edges and has a real-time self-calibration unit to ensure the adjustment accuracy of the delay line and prevent the gradient adjustment from crossing the low-resolution period and causing offset stability issues. This architecture uses a cascaded carry delay chain design and global PWM drive via a BUFG, enabling automatic global routing and improving system portability. Experimental results demonstrate that the high-resolution delay units of this architecture are all below 100 ps, with an average delay of 67 ps, and it has high linearity and monotonicity.