本文采用4T GC-eDRAM存储单元设计了面向低温应用的可编程存算一体电路。首先提出了双字线读出结构避免了存储单元的数据破坏问题；其次依据计算数据分布集中于零的特点，提出了强零编解码电路进一步降低电路的读出功耗；最后提出了可编程的近存计算电路，其能够支持逻辑运算、加减乘除等算术运算。采用TSMC 65nm低功耗工艺进行了设计验证，实验表明该存算一体电路对卷积运算加速比最高达到6倍，轻量级数据加密加速比达到12.3倍。在-40℃到85℃范围内，读写与计算能效比超过6T SRAM结构。值得注意的是，由于本电路基于GC-eDRAM设计，其性能与漏电流和刷新频率强相关。当温度进一步降低到液氮温区（如77K）时， 晶体管的漏电被急剧抑制，刷新周期可大幅延长，电路的性能得到极致发挥，这使得设计的电路在低温计算方面有着巨大的优势。

This paper presents a programmable computing-in-memory circuit based on a 4T GC-eDRAM cell, designed for cryogenic applications. First, a dual word-line readout structure is proposed to prevent data corruption in the memory cell. Second, leveraging the characteristic that computational data is often zero-biased, a zero-enhancement decoder/encoder circuit is proposed to further reduce read power consumption. Finally, a programmable near-memory computing circuit is implemented, capable of supporting both logic operations and arithmetic operations such as addition, subtraction, multiplication, and division. The design was fabricated and verified using a TSMC 65nm low power process. Experimental results demonstrate that the proposed circuit achieves a maximum speedup of 6× for convolution operations and 12.3× for lightweight data encryption. Within the temperature range of -40°C to 85°C, the circuit exhibits superior read, write and computing energy efficiency compared to a 6T SRAM structure. It is worth noting that, as this circuit is based on a GC-eDRAM design, its performance is closely linked to leakage current and refresh frequency. As the temperature is lowered further into the liquid nitrogen range (77 K), the leakage current of MOS transistors is drastically reduced, enabling the refresh cycle to be significantly extended. This maximizes the circuit's energy efficiency ratio, giving the designed circuit substantial advantages in low-temperature computing applications.