针对当前卫星通信终端在高吞吐IP业务场景下面临的处理性能瓶颈问题，本文提出一种基于CPU+FPGA SoC架构的高速IP业务传输方法。该方法核心在于控制面与数据面的分离与协同：将高速数据转发需要的IP接入、路由寻址、链路帧组/解帧等功能卸载至FPGA处理，形成高性能数据面；将路由维护、协议交互等控制面逻辑交由CPU完成。通过事件驱动同步、硬件级QoS调度等关键技术，克服了协同设计中表项同步、信令低时延保障等工程化难题，实现了在现有硬件上的性能显著跃升，为大规模在网卫星终端的平滑性能升级及小型化低功耗终端设计提供了有效解决方案。

Facing the processing performance bottleneck of current satellite communication terminals in high-throughput IP service scenarios, this paper proposes a high-speed IP service transmission method based on a CPU+FPGA SoC architecture. The core of this method lies in the separation and cooperation of the control plane and the data plane: functions required for high-speed data forwarding, such as IP access, route addressing, and link frame assembly/disassembly, are offloaded to the FPGA to form a high-performance data plane; control plane logic such as route maintenance and protocol interaction is handled by the CPU. Through key technologies like event-driven synchronization and hardware-level QoS scheduling, engineering challenges in collaborative design, such as entry synchronization and low-latency signaling guarantee, are overcome. This achieves a significant performance leap on existing hardware, providing an effective solution for the smooth performance upgrade of large-scale in-network satellite terminals and the design of compact, low-power terminals.