采用折叠式共源共栅与AB类输出相结合的两级运放，结合线性跨导环和输出阻抗自举技术设计了一款低偏置电流轨对轨的高增益、高带宽的运算放大器。第一级采用折叠式共源共栅结构，通过并联 NMOS 与 PMOS 输入差分对管实现轨对轨 输入，并通过适当的电流补偿设计确保第一级的恒定输出阻抗。第二级采用了 AB 类 输出方式，通过跨导线性环可精确控制输出级静态电流，实现较好的驱动能力并降低了功耗，使用Gain-boosting技术将 Cascode 结构的输出阻抗进一步提高进而增大增益。该运算放大器采用SMIC 180nm MS BCD CMOS工艺设计。流片后，自主设计测试电路，绘制PCB电路板从而搭建出测试平台，并利用示波器，网络分析仪和频谱分析仪测量了一款宽带低偏流运算放大器的输入偏置电流、失调电压、开环增益、小信号带宽、压摆率和噪声等关键主要参数。测试结果表明：在负载电容2pF时，运放的低频增益为50dB，增益带宽积为380MHz。

A two-stage operational amplifier with low input bias current, rail-to-rail input, high gain, and high bandwidth has been designed by combining a folded-cascode first stage with a class-AB output stage, incorporating a linear transconductance (Gm) loop and gain-boosting techniques. The first stage employs a folded-cascode architecture, achieving rail-to-rail input through parallel NMOS and PMOS input differential pairs. A dedicated current compensation scheme ensures a constant output impedance of the first stage. The second stage utilizes a class-AB output configuration, where a translinear loop precisely sets the quiescent current of the output stage, resulting in improved drive capability and reduced power consumption. Gain-boosting techniques are applied to further enhance the output impedance of the cascode structure, thereby increasing the overall DC gain. The op-amp is fabricated in a SMIC 180nm MS BCD CMOS process.After tape-out, a test platform was independently developed by designing the test circuitry and fabricating a custom PCB board. Key parameters of a broadband low-input-bias-current operational amplifier, including input bias current, offset voltage, open-loop gain, small-signal bandwidth, slew rate, and noise, were measured using an oscilloscope, network analyzer, and spectrum analyzer. Test results demonstrate that with a 2pF load capacitor, the amplifier achieves a low-frequency gain of 50dB and a gain-bandwidth product (GBW) of 380MHz.