基于FPGA的万兆以太网在雷达前端设计中的实现

唐浩

集成电路与嵌入式系统 ›› 0

集成电路与嵌入式系统 ›› 0 DOI: 10.20193/j.ices2097-4191.2025.0143

基于FPGA的万兆以太网在雷达前端设计中的实现

  • 唐浩
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Implementation of 10-Gigabit Ethernet Based on FPGA in Radar Front-End Design

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摘要

介绍了基于Xilinx公司FPGA的高速实时信号处理雷达数字前端设计。本雷达前端的FPGA充分利用其丰富的逻辑、RAM、DSP及高速接口等资源,实现万兆以太网、Microblaze和高速缓存等功能模块,这就使得该FPGA具有控制、预处理及高速数据传输功能,进而使得本雷达处理前端具有硬件结构简洁,信号处理能力高、数据传输速度快等特点。在软件实现中,还根据雷达波形特点,精心设计高速数据读写时序,使其数据传输能力达到设计要求。在监视雷达项目中得到了成功应用,取得了良好的效果

Abstract

This paper presents the design of a high-speed real-time signal processing radar digital front-end based on Xilinx FPGA.The FPGA in this radar front-end fully utilizes its abundant resources, including logic, RAM,DSP, and high-speed interfaces, to implement functional modules such as 10-Gigabit Ethernet, Microblaze, and high-speed cache. This enables the FPGA to perform control, preprocessing, and high-speed data transmission, resulting in a radar processing front-end with a simple hardware structure, high signal processing capability, and fast data transmission speed. In software implementation, the high-speed data read-write timing is meticulously designed according to radar waveform characteristics to meet the data transmission capacity requirements. It has been successfully applied in real-time processing for surveillance radar projects, achieving excellent results

关键词

FPGA / 雷达 / MTU / UDP / 万兆以太网 / Microblaze / SFDR

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唐浩. 基于FPGA的万兆以太网在雷达前端设计中的实现[J]. 集成电路与嵌入式系统. 0 https://doi.org/10.20193/j.ices2097-4191.2025.0143
Implementation of 10-Gigabit Ethernet Based on FPGA in Radar Front-End Design[J]. Integrated Circuits and Embedded Systems. 0 https://doi.org/10.20193/j.ices2097-4191.2025.0143

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