在面向高密度2T0C阵列的存内计算（CIM）中，阵列寄生电容主导了读写路径的电荷再分配与位线积分动态，是影响存储节点电压扰动和计算线性度的关键因素。然而，传统高精度寄生电容提取方法随阵列规模扩增而计算成本剧增，难以支撑阵列级建模与系统设计。为此，本文基于远端互连线的渐逝耦合特性，提出一种面向大规模2T0C阵列中心单元的高精度寄生电容近似提取方法。该方法通过聚合非临近字线/位线族，构建九端口等效网络；进而，在1%相对误差约束下，确定了关键寄生电容的截断距离并给出其定量表达式，从而实现了阵列级寄生电容的快速提取。基于此，本文建立了不同读写阶段存储节点电容C_SN与读位线电容C_RBL的高精度模型，准确捕捉了C_RBL随阵列规模近线性增长的特性。仿真验证表明，在阵列几何尺寸等比微缩10倍时，本文所提阵列级模型的提取精度相较于器件级模型提升了15%。进一步的分析表明，若采用低精度的器件级模型对电流域2T0C CIM方案进行线性度评估，会导致积分非线性峰值被高估约1.5 LSB。

In compute-in-memory (CIM) employing high-density 2T0C arrays, parasitic capacitances critically determine charge redistribution and bit line integration dynamics, directly impacting storage-node (SN) disturbance and computational linearity. However, the escalating computational cost of conventional extraction methods with array size obstructs efficient array-level modeling and system analysis. To address this, we propose a high-accuracy approximation method for extracting parasitics from the central cell of large-scale arrays by leveraging the attenuating coupling of long interconnects. The method constructs a nine-port aggregated equivalent network by bundling non-adjacent word/bit lines and derives a quantitative expression for the minimum truncation distance of key capacitances under a 1% relative-error bound, enabling rapid array-level (AM) parameter extraction. This facilitates high-accuracy models for the SN and bit line capacitances (C_SN and C_RBL) across operational phases, accurately capturing the near-linear scaling of C_RBL with array size. Simulations under 10× geometric scaling show a 15% accuracy improvement over the device-level model (DM). Crucially, linearity analysis based on this precise model reveals that using the low-accuracy DM would overestimate the peak integral non-linearity (INL) by approximately 1.5 least significant bit (LSB).