摘要
随着边缘人工智能(Artificial Intelligence, AI)技术的迅速发展,资源受限的终端对于神经网络推理的能效提出了更为苛刻的要求。然而,现有的多比特神经网络模型及其硬件电路普遍存在能耗高、结构复杂等问题,限制了其在低功耗场景下应用。因此,本文聚焦于边缘视觉任务中的轻量化推理需求,以二值化神经网络为代表,提出了一种面向卷积推理的低功耗存算一体电路设计方法。该方法基于电荷域耦合原理,设计了一种结构精简的10T1C-SRAM存算一体单元,并针对模拟输出特性开发低失调比较器和高效输入驱动电路,将五层二值化神经网络(Binarized Neural Networks, BNN)架构中的Conv2至Conv4三层卷积映射到存算一体(Computing-in-Memory, CIM)阵列中,从而实现对BNN中卷积计算的加速。同时,为了避免多层卷积计算中频繁的片外访问操作,通过滑动窗口驱动的数据调度机制完成推理流程。该架构由台积电180nm工艺实现,系统平均功耗为38.67μW,平均能效为243TOPS/W,整体性能优于多项同类低功耗存算架构。系统在微瓦级功耗下实现了三层卷积神经网络(Convolutional Neural Network, CNN)的推理,展现出较强的能效优势。
Abstract
With the rapid development of edge Artificial Intelligence (AI) technologies, resource-constrained terminals impose increasingly stringent requirements on the energy efficiency of neural network inference. However, existing multi-bit neural network models and their hardware implementations generally suffer from high power consumption and complex architectures, which limit their applica-bility in low-power scenarios. Therefore, this work focuses on the demand for lightweight inference in edge vision tasks and propos-es a low-power computing-in-memory (CIM) circuit design method for convolutional inference based on Binarized Neural Networks (BNNs).Based on the charge-domain coupling principle, a compact 10T1C-SRAM CIM cell is designed. To accommodate the ana-log output characteristics, a low-offset comparator and an efficient input driver circuit are further developed. In the proposed archi-tecture, three convolutional layers (Conv2–Conv4) of a five-layer BNN are mapped onto the CIM array to accelerate convolution operations in BNN inference. Meanwhile, to avoid frequent off-chip memory accesses during multi-layer convolution processing, a sliding-window-driven data scheduling mechanism is adopted to complete the inference process. The proposed architecture is im-plemented using the TSMC 180-nm CMOS process. The system achieves an average power consumption of 38.67 μ W and an aver-age energy efficiency of 243 TOPS/W, outperforming several existing low-power CIM architectures. The system enables the infer-ence of a three-layer Convolutional Neural Network (CNN) under microwatt-level power consumption, demonstrating significant energy-efficiency advantages.
关键词
存算一体 /
电荷域计算 /
二值神经网络 /
低功耗 /
边缘视觉感知
Key words
computing-in-memory /
charge-domain computing /
binarized neural networks /
low power /
edge vision sensing
徐祥, 魏淑华, 陈亮, 魏琦, 乔飞.
应用于边缘视觉BNN推理的存算一体电路设计[J]. 集成电路与嵌入式系统. 0 https://doi.org/10.20193/j.ices2097-4191.2026.0028
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基金
北京市自然科学基金资助(L253009); 国家自然科学基金项目(No. 62334006, U25A20489); 时空信息精密感知技术全国重点实验室开放基金(No.STSL2025-B-02-01(M))