一种高PSRR超低漏失的LDO设计

苏河, 唐威, 王景毅, 陈麟

集成电路与嵌入式系统 ›› 0

集成电路与嵌入式系统 ›› 0 DOI: 10.20193/j.ices2097-4191.2026.0044

一种高PSRR超低漏失的LDO设计

  • 苏河, 唐威, 王景毅, 陈麟
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Design of a High-PSRR and Ultra-Low Dropout LDO

  • SU He, TANG Wei, WANG yi Jing, CHEN Lin
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摘要

针对手机摄像头、蓝牙等噪声敏感电子设备的供电问题,设计了一种高电源纹波抑制比(Power Supply Rejection Ratio, PSRR )超低漏失电压的低压差线性稳压器(Low Dropout Regulator, LDO )。电路采用N型场效应晶体管(NMOS)作为调整管,通过双路电源供电,分离偏置电源与调整管输入电源,实现高PSRR与超低漏失电压。设计引入预稳压调制电路以及低通滤波器来处理基准电压,提高偏置电源的PSRR。主环路则通过反向嵌套密勒补偿调整系统零极点分布,提高电路整体的PSRR。基于0. 18μm CMOS工艺完成电路和版图的设计,电路最大负载电流为500mA,仿真结果表明,在最大负载电流下的漏失电压为100mV;在负载10mA时,100Hz、1kHz、10kHz、1MHz频率下输入电源的PSRR分别为-110dB、-90dB、-70dB、-65dB。

Abstract

Addressing the power supply issues of noise-sensitive electronic devices such as mobile phone cameras and Bluetooth, a low dropout regulator (LDO) with high power supply rejection ratio (PSRR) and ultra-low dropout voltage has been designed. The circuit employs an N-type field-effect transistor (NMOS) as the regulation transistor and is powered by a dual-power supply. It segregates the bias power supply from the input power supply of the regulation transistor, thereby attaining a high Power Supply Rejection Ratio (PSRR) and an ultra-low dropout voltage. The design incorporates a pre-regulation modulation circuit and a low-pass filter to process the reference voltage, enhancing the PSRR of the bias power supply. The main loop adjust the system's pole-zero distribution through inverse nested Miller compensation, improving the overall PSRR of the circuit. The circuit and layout design were completed based on a 0.18µm CMOS process. The maximum load current of the circuit is 500mA. Simulation results show that the dropout voltage at maximum load current is 100mV. At a load of 10mA, the power supply rejection ratio (PSRR) of the input power supply at frequencies of 100Hz, 1kHz, 10kHz, and 1MHz are -110dB, -90dB, -70dB, and -65dB, respectively.

关键词

高电源抑制比 / 超低漏失电压 / 低压差线性稳压器 / NMOS / 预稳压

Key words

High Power Supply Rejection Ratio / Ultra-Low Dropout / Low-Dropout Linear Regulator / NMOS / Pre-regulation

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导出引用
苏河, 唐威, 王景毅, 陈麟. 一种高PSRR超低漏失的LDO设计[J]. 集成电路与嵌入式系统. 0 https://doi.org/10.20193/j.ices2097-4191.2026.0044
SU He, TANG Wei, WANG yi Jing, CHEN Lin. Design of a High-PSRR and Ultra-Low Dropout LDO[J]. Integrated Circuits and Embedded Systems. 0 https://doi.org/10.20193/j.ices2097-4191.2026.0044

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