在180nm CMOS工艺节点下，标准单元库的多目标优化仍高度依赖SPICE仿真，导致严重的计算瓶颈。单次SPICE瞬态分析耗时约100 ms，典型库优化需10 000次以上迭代，8核并行仍需约2.1分钟。本文提出一种轻量级混合数据集替代模型框架，通过25个真实PySpice仿真样本（GF180MCU PDK）与130个开源基准数据融合，构建总计155样本的高效数据集。对比8种机器学习架构后，MLP模型在精度-速度权衡中表现最优（功耗预测R²=0.8734，延迟预测R²=0.9521），单次推理时间仅1μs，实现较传统SPICE约1 000 00倍加速。跨单元零样本测试显示平均R²达0.6746，仅需15个额外SPICE样本微调即可进一步提升性能。工业ROI分析表明，对于50人设计团队，设计周期从2.1分钟缩短至0.5分钟，3年累计净收益可观，ROI高达200–300%以上。本方法为AI驱动的电路设计自动化提供了可部署、高性价比的解决方案，具有显著工程价值与经济效益。

At the 180 nm CMOS process node, multi-objective optimization of standard-cell libraries still relies heavily on SPICE simulation, resulting in severe computational bottlenecks. A single transient analysis typically takes ~100 ms; a typical library optimization requiring over 10 000 iterations consumes approximately 2.1 minutes even with 8-core parallelization. This paper proposes a lightweight surrogate modeling framework that constructs a hybrid dataset of only 155 samples by fusing 25 high-fidelity PySpice simulations (GF180MCU PDK) with 130 open-source benchmark points. After systematically comparing eight machine-learning architectures, the multi-layer perceptron (MLP) model achieves the best accuracy-speed trade-off (R² = 0.8734 for power and 0.9521 for delay) with an inference time of only 1μs, delivering approximately 1 00 000× acceleration over conventional SPICE. Zero-shot cross-cell generalization yields an average R² of 0.6746; fine-tuning with merely 15 additional SPICE samples per new cell further improves performance. Industrial ROI analysis for a 50-engineer design team shows the design cycle reduced from 2.1 min to 0.5 min, with a 3-year net benefit yielding ROI of 200–300 %. The proposed approach provides a deployable, cost-effective solution for AI-assisted circuit design automation with substantial engineering and economic value.