脉冲神经网络以离散脉冲序列进行信息表示与处理，具有事件驱动与稀疏计算特性，具备实现高能效智能计算的潜力。为充分发挥其低功耗优势，面向SNN的专用硬件与神经形态芯片的实现技术具有重要研究意义。本文从硬件实现视角出发，围绕“神经元模型-信息编码方法-网络结构-硬件架构”的全链条，对SNN硬件实现研究进行系统梳理。文中阐述了常用脉冲神经元模型与信息编码方法，探讨了包括全连接、卷积与注意力机制的网络结构，重点对硬件架构等研究工作进行了系统性的归纳和总结，比较了不同电路实现技术与计算模式方案的优势与不足，分析了当前关键挑战并展望未来。

Spiking neural networks (SNNs) represent and process information using discrete spike trains, exhibiting event-driven and sparse computation characteristics and offering strong potential for energy-efficient intelligent computing. To fully exploit their low-power advantages, dedicated hardware implementation techniques and neuromorphic chips for SNNs are of significant research importance. From the perspective of hardware implementation, this paper systematically reviews the full hardware development chain of SNNs, covering neuron models, information encoding methods, network structures, and hardware architectures. The paper describes commonly used spiking neuron models and information encoding methods, discusses network structures including fully connected, convolutional, and attention-based architectures, systematically summarizes research on hardware architectures, compares the advantages and limitations of different circuit implementation technologies and computing paradigms, and analyzes current key challenges while outlining future research directions.