随着 FPGA 在高性能嵌入式计算与数据中心领域的广泛应用，PCIe 接口的数据传输带宽需求日益增长。Xilinx 提供的 XDMA IP 核作为主流高性能 DMA 方案，但在 Linux 系统下实际性能往往受限于操作系统复杂的内存管理机制。本文通过理论和建模分析的方式研究在标准 Linux 驱动模型中对XDMA传输性能影响的关键点，发现用户空间内存的“惰性分配”策略导致物理页面的分配与映射被延迟至 DMA 传输请求发起之后，频繁触发缺页异常并增加 TLB Miss，严重制约了高带宽传输的效率与确定性。为解决这一瓶颈，本文提出一种利用 mmap 系统调用高级参数的应用层内存预映射优化策略，该策略将物理内存的分配、页表建立及页面锁定操作前移至系统初始化阶段完成,从而将运行时开销前置化，显著提升后续内存访问效率。通过理论分析与实验结果表明，本策略较优化前，在默认TLB大小的条件下，数据传输速率提高了85.5%，并进一步研究了TLB 大小对XDMA传输的影响，对于构建高性能、低延迟的嵌入式异构系统具有重要参考意义。

With the widespread application of FPGAs in high-performance embedded computing and data centers, the demand for data transmission bandwidth via the PCIe interface is increasing. Xilinx's XDMA IP core, as a mainstream high-performance DMA solution, often has its actual performance limited by the complex memory management mechanism of the Linux system. This paper studies the key points affecting the XDMA transmission performance in the standard Linux driver model through theoretical and modeling analysis, and finds that the "lazy allocation" strategy of user-space memory causes the allocation and mapping of physical pages to be delayed until after the DMA transmission request is initiated, frequently triggering page faults and increasing the TLB miss rate, which seriously restricts the efficiency and determinacy of high-bandwidth transmission. This paper proposes an application layer memory pre-mapping optimization strategy that utilizes advanced parameters of the mmap system call. This strategy moves the physical memory allocation, page table establishment, and page locking operations forward to the system initialization stage, thereby reducing the runtime overhead and significantly improving the subsequent memory access efficiency. Theoretical analysis and experimental results show that this strategy increases the data transmission rate by 85.5% under the default TLB size compared to the optimized version. Furthermore, the impact of TLB size on XDMA transmission is studied, which is of great reference significance for building high-performance, low-latency embedded heterogeneous systems.