针对Opus音频编码器SILK模式中线性预测编码（Linear Predictive Coding，LPC）分析滤波器高频调用、运算量大及参数随子帧动态变化的问题，本文基于Zynq-7000 SoC平台设计并实现了一种可重构硬件加速器。该设计采用参数化转置型FIR全流水架构，结合DSP48E1资源优化，在稳态下可实现每时钟周期处理1个输入样本。为保证变长子帧切换过程中数据的一致性，引入Shadow/Active双缓冲参数更新机制，使滤波器参数在处理帧边界提交，避免同一处理帧内发生参数撕裂。通过AXI DMA构建高效软硬协同数据通路，并按照Opus定点运算规则完成硬件实现与验证。实验结果表明，该设计在XC7Z100平台上LUT占用率低于2.1%，在目标时钟频率下满足时序约束；宽带长帧典型配置下，相较于ARM Cortex-A9端开启编译优化的libopus定点C参考实现，算法核加速比达9.98倍，端到端平均加速比达3.82倍，硬件输出与软件参考模型保持逐样本位精确（Bit-Exact）一致。该设计在保证计算正确性的同时具备较低资源开销，可为资源受限嵌入式音频编码系统提供有效的硬件加速方案。

To address the issues of high-frequency calls, large computational load, and dynamic parameter changes with subframes in the Linear Predictive Coding (LPC) analysis filter of the Opus audio encoder's SILK mode, this paper designs and implements a reconfigurable hardware accelerator based on the Zynq-7000 SoC platform. This design employs a parameterized transposed FIR fully pipelined architecture, combined with DSP48E1 resource optimization, achieving one input sample per clock cycle in steady state. To ensure data consistency during variable-length subframe switching, a Shadow/Active double-buffered parameter update mechanism is introduced, ensuring filter parameters are committed at processing frame boundaries and preventing parameter tearing within the same processing frame. An efficient hardware-software co-processing data path is constructed using AXI DMA, and hardware implementation and verification are completed according to Opus fixed-point arithmetic rules. Experimental results show that the LUT utilization rate of this design is less than 2.1% on the XC7Z100 platform, and it meets timing constraints at the target clock frequency. Under typical wideband long frame configurations, compared with the optimized libopus fixed-point C reference implementation running on ARM Cortex-A9, the algorithm core speedup reaches 9.98 times, and the average end-to-end speedup reaches 3.82×. The hardware output maintains bit-exact consistency with the software reference model. This design has low resource overhead while ensuring computational correctness, and can provide an effective hardware acceleration solution for resource-constrained embedded audio coding systems.