设计了一种采用28 nm CMOS工艺实现的4~13 GHz可编程分频器。核心可编程分频器由7级多模分频器（MMD）核心（2/3预分频级和6级级联2/3单元）和内嵌固定二分频器构成。7位控制字解码为每个单元的2位配置信号（P1和P2），这些信号同时确定链长和分频操作模式。7级MMD核心实现连续整数分频比n=1~255。固定二分频器将总分频比扩展到2n，即2到510。正交二分频器在核心可编程分频器之后级联，将分频比进一步扩展到4n，即4到1020，并产生四相I/Q信号。所提出的双比特方案为级联链中的最后一个工作单元实现了独立的÷3模式，该模式下末级工作状态由配置字直接指定。PVT仿真验证了电路的鲁棒性。在13 GHz、最大分频比为1020条件下，分频器功耗为6.1 mW，1 kHz偏移处的相位噪声为-165 dBc/Hz。仿真在28 nm CMOS工艺、TT/SS/FF工艺角、-55 ℃/125 ℃/27 ℃温度条件下进行验证。

This paper presents a 4~13 GHz programmable divider implemented using a 28 nm CMOS process. The core programmable divider is composed of a 7-stage multi-mode divider （MMD） core （a 2/3 prescaler stage and six cascaded 2/3 units） and an embedded fixed divide-by-two stage. The 7-bit control word is decoded into 2-bit configuration signals （P1， P2） for each unit， which simultaneously determine the chain length and the division operation mode. The 7-stage MMD core achieves continuous integer division ratios from 1 to 255. The fixed divide-by-two stage extends the total division ratio to 2n， ranging from 2 to 510. An orthogonal divide-by-two stage cascaded with the core programmable divider further extends the division ratio to 4n， ranging from 4 to 1020， and generates four-phase I/Q signals. The proposed dual-bit scheme realizes an independent ÷3 mode for the last active unit in the cascaded chain， where the final stage operation state is directly specified by the configuration word. PVT simulations verify the the robustness of the proposed divider. At 13 GHz with a maximum division ratio of 1020， the divider consumes 6.1 mW of power， and the phase noise is -165 dBc/Hz at a 1 kHz offset. The simulation was performed using a 28-nm CMOS process across TT， SS， and FF process corners and temperatures of -55℃， 27℃， and 125℃.