面向14nm等 FinFET先进工艺节点，传统BSIM物理模型存在标定周期长、新型器件适配性差，查表模型精度不足等工程痛点，而当前基于机器学习的器件模型难以接入商用EDA仿真工具。本文创新性地提出ANN器件代理+随机森林电路代理双层协同优化完整流程（DTCO），为先进制程DTCO自动化落地提供了标准化技术方案。首先基于Sentaurus TCAD多维度仿真数据集，构建带批归一化、LeakyReLU激活的全连接人工神经网络，同步融合栅结构参数、老化应力、电压偏置等多类输入，精准预测FinFET漏电流与终端电荷电容；然后设计自动化解析转换工具，将训练完成的PyTorch网络导出为兼容Spectre/HSPICE的Verilog-A器件模型，打通机器学习模型与SPICE仿真链路；最后，采用拉丁超立方采样遍历器件-电路耦合高维设计空间，批量仿真后训练随机森林轻量化电路代理模型，替代耗时重复电路仿真；依托NSGA-III多目标进化算法，以全加器单元延迟、功耗为优化目标，求解帕累托最优解集。实验结果表明：FinFET器件ANN模型测试集决定系数R2=0.996，相较原生TCAD仿真提速105倍；分层代理模型协同优化流程整体加速30倍；优化后设计可实现同等功耗下延迟降低22%，同等延迟下功耗降低31%。所提流 程可完整实现含可靠性老化变量的器件-工艺-电路跨层联合优化，为先进制程DTCO自动化落地提供标准化技术方案。

For the 14nm FinFET advanced process node, traditional BSIM physical models have long calibration cycles and poor adaptability to new devices, lookup table models have insufficient accuracy, and machine learning device models are difficult to access commercial EDA simulation tools. This paper proposes a complete two-layer collaborative DTCO optimization process of ANN device proxy + random forest circuit proxy. First, a fully connected artificial neural network with batch normalization and LeakyReLU activation is built based on the Sentaurus TCAD multi-dimensional simulation dataset, integrating gate structure parameters, aging stress, and electrical bias inputs to accurately predict FinFET leakage current and terminal charges. An automated parsing and conversion tool is designed to export the trained PyTorch network into a Verilog-A device model compatible with Spectre/HSPICE, connecting the machine learning model with the SPICE simulation link. Latin hypercube sampling is used to traverse the high-dimensional design space of device-circuit coupling, and after batch simulation, a random forest lightweight circuit proxy model is trained to replace time-consuming repeated circuit simulations. Based on the NSGA-III multi-objective evolutionary algorithm, the Pareto optimal solution set is solved with the full-adder unit delay and power consumption as optimization objectives. Experimental results show that the test set determination coefficient of the FinFET device ANN model is R2=0.996, which is 105 times faster than the native TCAD simulation; the overall acceleration of the hierarchical proxy model collaborative optimization process is 30 times; the optimized design can achieve a 22% reduction in delay under the same power consumption and a 31% reduction in power consumption under the same delay. The proposed process can fully realize cross-layer joint optimization of device-process-circuit including reliability aging variables, providing a standardized technical solution for the automated implementation of advanced process DTCO automation.