针对模拟电路尺寸优化中设计空间维度高、仿真代价高以及有限样本下搜索效率下降等问题，提出一种基于动态融合采集函数的贝叶斯优化算法。算法采用拉丁超立方采样构造初始样本，并结合截断高斯子空间采样生成候选点，根据搜索结果调整搜索中心、采样步长和协方差结构；针对局部样本较少时高斯过程超参数估计易受初值和局部极值影响的问题，引入超参数先验构建最大后验估计目标，并采用多起点L-BFGS算法求解；候选点选择阶段利用Sigmoid权重动态融合上置信界与期望改进，使两种采集函数的贡献随仿真进程变化，搜索策略由前期全局探索逐步转向后期局部开发。三个实际模拟电路的优化结果表明，与tSS-BO相比，所提算法获得的可行设计点数量最高为其1.46倍，优化目标最高改善19.95%，在有限仿真预算下具有较好的搜索效率和收敛稳定性。

Analog circuit sizing involves high-dimensional design spaces, costly simulations, and limited samples, which often reduce Bayesian optimization efficiency. A Bayesian optimization algorithm with dynamically fused acquisition functions is proposed. Latin hypercube sampling is used for initialization, while truncated Gaussian subspace sampling generates candidate points. The search center, step size, and covariance structure are updated from previous evaluations. For local Gaussian-process modeling, hyperparameter priors are introduced to form a maximum a posteriori objective, solved by multi-start L-BFGS to reduce sensitivity to initialization and local optima. During candidate selection, sigmoid weights dynamically combine upper confidence bound and expected improvement ac-cording to simulation progress, allowing the search to shift gradually from global exploration to local exploitation. Tests on three practical analog circuits show that, compared with tSS-BO, the proposed algorithm obtains up to 1.46 times as many feasible designs and improves the optimization objective by up to 19.95%, with efficient and stable convergence under limited simulation budgets.