基于RISCV标准指令集,提出一种六级流水线设计方法。首先,分析了流水线级数对处理器性能的影响,在经典五级流水线的基础上将流水线划分为6个阶段,缩短时延,提高主频。其次,为解决流水线中的冒险问题,采用定向前推和插入纵向气泡的方式处理数据冒险问题,使用流水线冲刷解决流水线中控制冒险问题。最后,在EDA工具中,采用RISCV标准指令集对本设计进行仿真测试,并在FPGA上实现,运行时钟频率可达78.2 MHz。
Abstract
Based on the RISCV standard instruction set,a six-stage pipeline design is designed in the paper.First of all,this article analyzes the impact of pipeline stages on processor performance,and divides the pipeline into six-stage on the basis of the classic five-stage pipeline,reducing the delay to improve the main frequency.Secondly,in order to solve the risk problem in the pipeline,this design adopts the method of pushing forward and inserting longitudinal bubbles to deal with the data adventure problem,and uses the pipeline flushing to solve the control risk problem in the pipeline.Finally,in the EDA tool,the design is simulated using the RISCV standard instruction set and implemented on the FPGA,running at clock frequencies up to 78.2 MHz.
关键词
RISCV /
处理器架构 /
流水线 /
数据冒险
Key words
RISCV /
processor architecture /
pipeline /
data hazards
{{custom_sec.title}}
{{custom_sec.title}}
{{custom_sec.content}}
参考文献
[1] 何小庆.RISCV产业的现状与未来[J].单片机与嵌入式系统应用,2021,21(8):3.
[2] 刘畅,武延军,吴敬征,等.RISCV指令集架构研究综述[J].软件学报,2021,32(12):39924024.
[3] Zoni Davide,Galimberti Andrea.Costeffective fixedpoint hardware support for RISCV embedded systems[J].Journal of Systems Architecture,2022(126).
[4] 怯肇乾,官莉萍,张晓强,等.RISCV指令集及其微控制处理器的开发应用[J].单片机与嵌入式系统应用,2021,21(8):913.
[5] 贾琳,樊晓桠.32位RISC微处理器流水线设计[J].计算机工程与应用,2005(14):115117.
[6] 折如义,李炳辉,姜佩贺.三级流水线RISCV处理器设计与验证[J].电子技术应用,2020,46(5):4449.
[7] 江兵,吴敏.FPGA开发板上的ARM软核构建[J].单片机与嵌入式系统应用,2022,22(3):6973.
[8] Mantovani P,Margelli R,Giri D,et al.HL5:A 32bit RISCV Processor Designed with HighLevel Synthesis[C]//Proceedings of the Custom Integrated Circuits Conference,2020(3).
[9] 刘览,郑步生,施慧彬.基于FPGA的32位RISC微处理器设计[J].数据采集与处理,2011,26(3):367373.
[10] 冯海涛,王永纲,石江涛,等.基于FPGA的32位整数微处理器的设计与实现[J].小型微型计算机系统,2005(6):11131117.
[11] 史大龙,唐建,周远远,等.一种基于ASIC实现的流水线架构8051内核设计[J].微型机与应用,2013,32(8):1820.
PDF(1136 KB)
