出于对信号发生器性能、设计成本等方面的考虑,本文基于FPGA设计了精度高、稳定性强的DDS信号发生器。通过Verilog HDL语言对FPGA编程,构建DDS功能模块,实现基本数字频率合成功能。设计从三方面进行考量,即供电端电源调理电路、FPGA内部进行DDS杂散抑制以及输出端波形信号调理和滤波电路,尽可能抑制电路中噪声干扰和DDS信号调制产生的杂散问题。经过验证,该方案生成波形有效值误差为10 mV,纹波大小为10.20 mV,能实现高精度、高稳定性的信号发生器。

Considering the performance and design cost of signal generator,DDS signal generator with high precision and strong stability will be designed based on FPGA.FPGA is programmed by Verilog HDL language to build DDS function module and realize basic digital frequency synthesis function.The design is considered from three aspects,namely,power conditioning circuit at the power supply end,DDS spurious suppression inside FPGA and waveform signal conditioning and filtering circuit at the output end,so as to suppress the spurious problems caused by noise interference and DDS signal modulation in the circuit as far as possible.After verification,the effective value error of the waveform generated by this scheme is 10 mV,and the ripple size is 10.20 mV.It can realize a high-precision and high stability signal generator.