[1] https://www.geeksforgeeks.org/microarchitecture-and-instruction-set-architecture/.
[2] https://en.wikipedia.org/wiki/RISCV.
[3] RISCV Reference.https://raw.githubusercontent.com/jameslzhu/riscv-card/master/riscv-card.pdf.
[4] https://en.wikipedia.org/wiki/Hardware_description_language.
[5] https://pulp-platform.org/.
[6] https://github.com/openhwgroup/cv32e40p.
[7] 基于SystemVerilog的CV32E40P指令解码器实现.https://github.com/openhwgroup/cv32e40p/blob/master/ rtl/cv32e40p_id_stage.sv.
[8] https://github.com/riscv-boom/riscv-boom.
[9] https://www.sifive.com/.
[10] https://scs.sifive.com/core-designer/.
[11] https://www.seagate.com/innovation/risc-v/.
[12] https://www.westerndigital.com/company/innovations/risc-v.
[13] http://tice.sea.eseo.fr/riscv/.
[14] https://www.crowdsupply.com/sifive/hifive1-rev-b.
[15] https://sifive.cdn.prismic.io/sifive%2F59a1f74e-d918-41c5-b837-3fe01ba7eaa1_fe310-g002-manual-v19p05.pdf.
[16] https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga.
[17] ChaCha算法:https://en.wikipedia.org/wiki/Salsa20#ChaCha_variant.
[18] https://en.wikipedia.org/wiki/Stream_cipher.

[19] https://www.imperas.com/sites/default/files/documents/Imperas_RISCV_Custom_Instruction_Flow_Application_Note.pdf.
[20] https://riscv.org/about/.
[21] https://riscv.org/membership/.
[22] https://riscv.org/members/.
[23] 兆易创新GD32 RISCV微控制器.https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/.
[24] 来自俄罗斯、基于RISCV的针对智能电表的K1986BK025微控制器:https://habr.com/en/company/milandr/blog/533322/.
[25] http://micromagic.com/.
[26] 关于阿里巴巴XT910 64位RISCV核的更多信息. https://www.european-processor-initiative.eu/.