基于RISC-V指令集架构实现了一种指令自动对齐电路。该电路可以将指令缓存发送过来的32位指令数据进行分解,从中解析出正确的指令。当指令缓存发送过来的32位指令数据对应的地址不是4字节对齐时(地址的低两位不是00)时,该电路可以自动将下一拍取指令数据的地址对齐到4字节,同时给出指令是否有效的指示标识;当指令地址4字节对齐时,该电路对指令数据进行分析,给出指令有效的标识、指令和对应指令的实际地址。给出的指令对齐电路的延时为4级两输入逻辑门,适用于高频标量处理器的前端取指令电路。
Abstract
Based on RISC-V instruction architecture,this article implements an instruction aligning circuit.This circuit can recognize and output the correct instruction by analyzing the 32-bit instruction data passed from the I-Cache.When the address of the 32-bit instruction data is not aligned with 4-Byte,say the two least significant bits of the address is not equal to 00,this circuit automatically aligns the address of the next instruction-fetching with 4-Byte and output the signal that indicating whether the instruction is valid or invalid.When the address of the instruction data is aligned with 4-Byte,this circuit presents the instruction,the real address of this instruction,and indicates that the instruction is valid.The latency of the circuit for aligning the instruction address to 4-Byte presented in this article is 4 levels of 2-inputs logic gates,which is very useful for the front-end instruction fetch circuit of high frequency scalar processor.
关键词
RISC-V /
指令对齐 /
微架构 /
内核流水线
Key words
RISC-V /
instruction align /
architecture /
pipeline of core
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参考文献
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基金
* 江苏省产业前瞻与关键核心技术重点项目(BE2019003)。
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