除法是4种基本算术运算中最复杂的一种,基于IP的可复用方法具有灵活、快速等优点,广泛应用在FPGA设计中。在FPGA中实现除法运算主流方法是采用厂家提供的IP,而在特定的应用中,IP有可能存在硬件木马等安全隐患。通过研究某除法器IP的算法架构、功能等,设计了一个兼容IP的除法模块。仿真结果验证了除法模块在功能、性能、资源占用等方面与除法器IP相当,该方法适合于对软件国产和替代有特殊需求的设计,亦可应用到其他IP的替代设计中。
Abstract
Division is the most complex of the four basic arithmetic operations.IP is widely used in FPGA design due to its agility and reuse.The most common form of division implemetaion is using specific IP which is provided by EDA vendors,and hardware trojans can be inserted into IP during system design.A compatible approach is presented by analyzing algorithm and function of the division IP.The simulation results show that compatible division is quite equal to IP in performance and resource utilization.The proposed scheme is also suitable for software domestic replacement and other IP compatible design.
关键词
除法器IP /
FPGA /
LUT /
WNS /
WHS
Key words
division IP /
FPGA /
LUT /
WNS /
WHS
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