针对Flip Chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添加参考平面而使信号具有完整的回流路径,使得传输线的阻抗在平面分割处由167.5 Ω降至52.5 Ω;对于因布线密度过大而造成的走线之间的串扰系数偏高的问题,通过减小板材的介质厚度使传输线间串扰系数的最大值从17.26%降至14.01%。仿真结果表明,此设计方法有效降低了芯片设计中潜在的信号完整性风险,提高了芯片的可靠性和稳定性。

In the process of designing Flip Chip packaged chips,there are issues such as discontinuities in transmission line impedance and excessive crosstalk.In the paper,a simulation analysis and design method based on impedance and crosstalk is proposed from two aspects of stack setting and plate medium thickness,which mainly involves two aspects:for the impedance mutation problem caused by the signal plane of reference being divided,the signal has a complete return path by adding a plane of reference,so that the impedance of the transmission line at the plane division is reduced from 167.5 Ω to 52.5 Ω.For the problem of high crosstalk coefficient between lines caused by excessive wiring density,the maximum crosstalk coefficient between transmission lines is reduced from 17.26% to 14.01% by reducing the dielectric thickness of the plate.The analysis and simulation results show that the method effectively reduces the potential signal integrity risk in chip design,and improves the reliability and stability of the chip.