一种基于FPGA的智能多主单总线

陈某舟, 郑小军

集成电路与嵌入式系统 ›› 2023, Vol. 23 ›› Issue (3) : 39-41.

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PDF(1172 KB)
集成电路与嵌入式系统 ›› 2023, Vol. 23 ›› Issue (3) : 39-41.
技术纵横

一种基于FPGA的智能多主单总线

  • 陈某舟, 郑小军
作者信息 +

Smart Multi-Master Single Bus Based on FPGA

  • Chen Mouzhou, Zheng Xiaojun
Author information +
文章历史 +

摘要

设计并实现了一种基于FPGA的智能多主单总线——Smart Multi-Master Single Bus。这种新型总线可广泛应用于工业控制领域和电力系统继电保护领域。基于FPGA的SM2总线不需要握手信号,采用自主收发机制,收发透明,具有智能、多主、高速、节约引脚、节约面积、低成本的优点,可挂接多种插件、总线设备,实现各插件、各总线设备之间自由、高速、高效的通信。

Abstract

An FPGA-based intelligent multi-master single bus—Smart Multi-Master Single Bus is designed and implemented.This new type of bus can be widely used in industrial control and power system relay protection.The SM2 bus based on FPGA does not need handshake signals,adopts the mechanism of independent transceiver,transmits and receives transparently.It has the advantages of intelligence,multi-master,high speed,pin saving,area saving,and low cost,and can be connected to a variety of plug-ins and bus devices to achieve free high-speed and efficient communication between plug-ins and bus devices.

关键词

FPGA / SM2 / 多主单总线

Key words

FPGA / SM2 / Multi-Master Single Bus

引用本文

导出引用
陈某舟, 郑小军. 一种基于FPGA的智能多主单总线[J]. 集成电路与嵌入式系统. 2023, 23(3): 39-41
Chen Mouzhou, Zheng Xiaojun. Smart Multi-Master Single Bus Based on FPGA[J]. Integrated Circuits and Embedded Systems. 2023, 23(3): 39-41
中图分类号: TN791   

参考文献

[1] Pango Design Suite 用户手册 V3.0,2020.
[2] Allwinner.T3 User Manual(V1.0),2016.
[3] MX3078E产品信息,2021.
[4] Zynq-7000 All Programmable SoC,2019.
[5] Clifford E Cummings.Simulation and Synthesis Techniques for Asynchronous FIFO Design[C]//SNUG 2002 (Synopsys Users Group Conference, San Jose,CA,2002) User Papers,March 2002,Section TB2,2nd paper.
[6] Philip Simpson.FPGA DESIGN-Best Practices for Team-based Design,2010.

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