分析了SM3密码杂凑算法基本流程,基于FPGA平台设计开发该算法的高性能硬件实现。以Xilinx公司ARTIX-7系列XC7A100T芯片为核心,采用16个寄存器构成寄存器组作为生成132个字的缓存区,设计进位保留加法器进行关键路径的压缩,使完成一次压缩函数中关键路径计算所需的时钟周期明显减少。实验结果表明,本文方案的吞吐率高达90.54 Gb/s,适用于对吞吐量有较高要求的场景。
Abstract
The basic flow of SM3 cryptographic hash algorithm is analyzed,a high-performance hardware implementation of SM3 on the field programmable gate array (FPGA) platform is designed.ARTIX-7 series chip of Xilinx is used as the core.We use a cache of 16 registers in a register group.The carry reservation adder is used to compress the critical path,which reduces the clock cycle to complete the critical path calculation in a compression function.The test results show that the throughput rate of the proposed scheme is up to 90.54 Gb/s,which is suitable for scenarios with high throughput requirements.
关键词
密码杂凑算法 /
SM3 /
FPGA /
XC7A100T
Key words
cryptographic hash algorithm /
SM3 algorithm /
FPGA /
XC7A100T
{{custom_sec.title}}
{{custom_sec.title}}
{{custom_sec.content}}
参考文献
[1] 杨波,现代密码学[M].4版.北京:清华大学出版社,2017.
[2] 王晓燕,杨先文.基于FPGA的SM3算法优化设计与实现[J].计算机工程,2012,38(6):244-246.
[3] 刘宗斌,马原,荆继武,等.SM3哈希算法的硬件实现与研究[J].信息网络安全,2011(9):191-193,218.
[4] 蔡冰清,白国强.SM3杂凑算法的流水线结构硬件实现[J].微电子学与计算机,2015,32(1):15-18.
[5] 方轶,丛林虎,邓建球,等.基于FPGA的SM3算法快速实现方案[J].计算机应用与软件,2020,37(6):259-262.
[6] 国家密码管理局SM3密码杂凑算法[EB/OL].[2022-12].http://www.oscca.gov.cn/UpFile/201012221418577866.pdf.
[7] 丁冬平,高献伟.SM3算法的FPGA设计与实现[J].微型机与应用,2012,31(5):26-28.
[8] 武迪,徐同阁,王子钰,等.集成消息填充的SM3算法硬件设计与实现[J].武汉大学学报(理学版),2019,65(2):218-222.
[9] 王晓燕,杨先文.基于FPGA的SM3算法优化设计与实现[J].计算机工程,2012,38(6):244-246.
[10] 蔡冰清,白国强.基于FPGA的HMAC-SM3硬件实现[J].微电子学与计算机,2015,32(7):17-19,24.
[11] 陈博宇,王宏.基于FPGA的SM3算法的优化实现[J].信息技术,2018,42(7):143-147.
[12] Huang Xiaoying,Guo Zhichuan,Song Mangu,et al.Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture[J].IET Computers & Digital Techniques,2021,15(6).
PDF(1169 KB)
