针对并行信号处理和传输资源消耗大的问题,利用高速RapidIO总线将多核DSP全互连,数据通过内存映射共享,8个核可分别并行传输和处理数据,轻量级包头的RapidIO块传输速率高、复制数据少、效率高。经验证大大提高了数据吞吐率、减少了传输时延,解决了传统FPGA器件实现并行计算编译时间长、调试困难、价格昂贵等问题,可推广到雷达信号脉冲压缩、SAR图像处理、分布式智能云计算等领域。
Abstract
Aiming at the problem of parallel signal processing and large consumption of transmission resources,the high-speed RapidIO bus is used to fully interconnect multi-core DSP,and the data is shared through memory mapping.Eight cores can transmit and process data in parallel respectively.The RapidIO block with lightweight header has high transmission rate,few data copies and high efficiency.It has been proved that the data throughput has been greatly improved,the transmission delay has been reduced,and the problems such as long compilation time,difficult debugging,and high price in parallel computing of traditional FPGA devices have been solved.It can be extended to radar signal pulse compression,SAR image processing,distributed intelligent cloud computing and other fields.
关键词
TMS320C6678 /
全互连 /
内存映射 /
并行计算 /
RapidIO
Key words
TMS320C6678 /
fully interconnect /
memory mapping /
parallel computing /
RapidIO
{{custom_sec.title}}
{{custom_sec.title}}
{{custom_sec.content}}
参考文献
[1] 邵龙.一种多DSP的SAR信号处理平台设计[J].电子设计工程,2020,28(1):172-175.
[2] 魏勐.一种阵列式DSP结构在雷达信号处理的应用[J].现代电子技术,2010(15):58-59.
[3] 康国胜.云计算与信息资源共享管理[J].科技创新导报,2020(17):126-127.
[4] 陈芳兰,姜宗田.TMS320C6678高速串行接口SRIO的设计与实现[J].通信设计与应用,2019(9):89-90.
[5] 张剑峰,周伟.基于综合一体化数字平台的VPX总线网络交换设计[J].数字通信世界,2020(6):71-72.
[6] 朱道山.基于RapidIO块数据传输设计与实现[J].现代雷达,2017(9):29-32.
[7] 武庆钊,吕林森.基于共享内存的多进程任务系统软件设计[J].航空电子技术,2021,52(4):44-49.
[8] 杨磊,张莹.基于TI多核DSP TMS320C6678的BOOT方式研究[J].数字技术与应用,2019,37(1):54-55.
[9] 高逸龙.RapidIO总线的嵌入式异构平台通信中间件[J].单片机与嵌入式系统应用,2020(2):19-26.
[10] 王晨,刘学纵.基于系统内核与共享内存的守护进程实现研究[J].工业控制计算机,2020,33(3):115-121.
[11] 邢慧敏,谢憬.一种多核系统中的二维块数据存储机制[J].计算机工程,2011,37(10):252-254.
[12] 李金明,高德亮.基于FPGA+DSP新型架构信号协同处理方案分析[J].兰州石化职业技术学院学报,2020,20(3):16-18.
[13] 李辉.一种跳频信号解调的多核DSP设计方法[J].电子设计工程,2020,29(1):158-163.
[14] 潘灵.RapidIO高性能通信中间件设计[J].电子技术应用,2014,40(12):107-109.
[15] 胥保春,李佩娟.基于数据采集卡的多通道阵列信号采集系统设计[J].电子设计工程 2019,27(8):170-173.
PDF(1025 KB)
