提出了一种基于输入/输出缓冲区信息规范的FPGA的TID效应建模方法。将FPGA电路结构划分为3部分:输入缓冲区、输出缓冲区、逻辑功能区。缓冲区模型基于IBIS模型使用VHDL-AMS建立,功能区模型基于特定需求采用VHDL建立。针对基于IBIS模型的建模需要,测量了FPGA在0 krad(Si)、820 krad(Si)和2.52 Mrad(Si)的IBIS模型和端口电平数据。通过对比仿真结果和试验结果,验证了所建模型能够反映FPGA受TID效应影响后的电平转换时间变长现象,结果误差在30%以内。所提建模方法为评估数字器件的TID效应提供了模型支撑,对数字系统抗辐射加固具有一定参考意义。
Abstract
A method for modeling the TID effect of FPGA is proposed based on the Input/Output Buffer Information Specification (IBIS).The structure of the FPGA circuit is divided into three parts:the input buffer,the output buffer and the logic functional area.The buffer model is modeled using VHDL-AMS based on the IBIS model,and the functional area model is developed using VHDL based on specific requirements.The IBIS model and port level data for the FPGA at 0 krad(Si),820 krad(Si) and 2.52 Mrad(Si) are measured for the IBIS model based modeling requirements.Comparison of the simulations with the experimental data shows that the proposed model reflects the effect of a longer level transition time after the FPGA is impacted by the total dose effect,and the error between the simulated and experimental results is within 30%.The proposed modeling method provides model support for evaluating the TID effect of digital components and is valuable for anti-radiation of digital systems.
关键词
FPGA /
总剂量效应 /
IBIS模型 /
混合信号模型 /
电平转换时间
Key words
FPGA /
total inoizing dose /
IBIS Model /
mixed signal model /
level transition time
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