静态时序分析主要依赖于时序模型和时序约束,是数字芯片时序验证的重要方法,其中时序约束是用来描述设计人员对时序的要求,如时钟频率、输入/输出延迟等。正确的时序约束可以缩短芯片设计周期,更快更好地完成静态时序分析。针对一款数据存储SoC芯片中的多时钟域异步设计要求,以及如何正确处理时序约束存在的问题,提出一种多分组异步时钟的全芯片时序约束,采用虚假路径、多时钟域分组、禁用单个寄存器多时钟分析设置等方法修复和优化设计规则、建立时间和保持时间违例,解决SoC存储芯片静态时序分析中的时序问题,保证所有时序路径正常满足时序逻辑功能要求,完成时序收敛,达到签核标准。

Static timing analysis mainly relies on timing models and timing constraints,which are important methods for timing verification of digital chips nowadays,where timing constraints are used to describe the designer's requirements for timing,such as clock frequency,input and output delays,etc.Correct timing constraints can shorten the chip design cycle and complete static timing analysis faster and better.For a data storage SoC chip in the multi-clock domain asynchronous design requirements,and how to correctly deal with the timing constraints exist,the paper proposes a multi-group asynchronous clock full-chip timing constraints.The false paths,multi-clock domain grouping,disable the single register multi-clock analysis settings are used to repair and optimize the design rules,build time and hold time violations.It solves the SoC memory chip static timing analysis in the timing problems,and ensures that all timing paths normally meet the timing logic function,completes the timing convergence,that meets the standards of the signed core.