针对集成电路产业快速发展所需要的复杂通信要求,设计了一种基于bit-map算法的DMA数据流仲裁器。DMA数据流仲裁器由通道优先级bit-map映射模块、通道请求生成模块、通道请求仲裁模块、通道授权标志生成模块和外设请求应答模块组成。在完成逻辑设计后,通过UVM验证方法学对电路的各个功能进行验证。验证结果表明,本设计仅使用一个32位bit-map映射寄存器将8条通道的32种优先级配置映射到对应有效位,便可实现对8条通道DMA请求的仲裁,无需配置优先级比较电路,不会因逐级比较产生优先级配置相互干扰的问题,且在后期生成实际电路的过程中可以减小电路面积、降低电路功耗。

Aiming at the complex communication requirements of the rapid development of integrated circuit industry,a DMA data stream arbiter based on bit-map algorithm is designed.DMA data flow arbiter is composed of channel priority bit-map mapping module,channel request generation module,channel request arbitration module,channel authorization flag generation module and peripheral request response module.After completing the logic design,each function of the circuit is verified by the UVM verification methodology.The verification results show that the design only uses a 32-bit bit-map register to map 32 kinds of priority configurations of 8 channels to the corresponding significant bits,so that the arbitration of DMA requests of 8 channels can be realized.There is no need to configure the priority comparison circuit,and the problem of mutual interference of priority configurations will not be generated due to the step by step comparison.In addition,the circuit area and power consumption can be reduced in the later process of generating the actual circuit.